| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 297 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
689 case X86II::MRM6r: case X86II::MRM7r: in getMemoryOperandNo()
|
| D | X86MCCodeEmitter.cpp | 899 case X86II::MRM6r: case X86II::MRM7r: in EmitVEXOpcodePrefix()
1404 case X86II::MRM6r: case X86II::MRM7r: { in encodeInstruction()
|
| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
722 case X86Local::MRM6r: in emitInstructionSpecifier()
856 case X86Local::MRM6r: case X86Local::MRM7r: in emitDecodePath()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrMMX.td | 488 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
491 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
494 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
|
| D | X86InstrFPStack.td | 287 def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">;
288 def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">;
289 def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">;
605 def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg),
607 def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg),
|
| D | X86InstrInfo.td | 1069 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1071 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1124 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1667 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1670 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1673 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
2044 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
2047 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
2050 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2405 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
[all …]
|
| D | X86InstrArithmetic.td | 298 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
301 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
304 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
308 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
1195 defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
|
| D | X86InstrSystem.td | 456 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
|
| D | X86InstrSSE.td | 4101 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4104 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4107 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4148 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4151 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4154 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4195 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4198 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4201 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
|
| D | X86InstrFormats.td | 32 def MRM6r : Format<22>; def MRM7r : Format<23>;
|
| D | X86InstrAVX512.td | 4088 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4089 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
|
| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 54 def MRM6r : Format<22>; def MRM7r : Format<23>;
|
| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1823 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
|