| /external/boringssl/src/ssl/test/runner/poly1305/ |
| D | poly1305_arm.s | 61 MOVM.DB.W [R4, R5, R6, R7, R8, R9, g, R11, R14], (R13)
66 MOVW R1, R14
82 MOVW_UNALIGNED(R14, g, R0, 0)
83 MOVW_UNALIGNED(R14, g, R0, 4)
84 MOVW_UNALIGNED(R14, g, R0, 8)
85 MOVW_UNALIGNED(R14, g, R0, 12)
87 ADD $16, R14
90 MOVM.IA.W (R14), [R0-R3]
95 MOVW R14, 40(R13)
109 ADD $64, R13, R14
[all …]
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| /external/boringssl/src/ssl/test/runner/curve25519/ |
| D | ladderstep_amd64.s | 23 MOVQ R14,24(SP)
84 MOVQ AX,R14
98 ADDQ AX,R14
107 ADDQ AX,R14
146 SHLQ $13,R15:R14
147 ANDQ DX,R14
148 ADDQ R13,R14
165 ADDQ R14,CX
199 MOVQ AX,R14
213 ADDQ AX,R14
[all …]
|
| D | mul_amd64.s | 25 MOVQ R14,24(SP)
57 MOVQ AX,R14
73 ADDQ AX,R14
90 ADDQ AX,R14
108 ADDQ AX,R14
136 ADDQ AX,R14
147 SHLQ $13,R15:R14
148 ANDQ SI,R14
149 ADDQ R13,R14
165 ADDQ R14,DX
[all …]
|
| D | square_amd64.s | 24 MOVQ R14,24(SP)
46 MOVQ DX,R14
60 ADCQ DX,R14
99 ADCQ DX,R14
109 SHLQ $13,R14:R13
114 ADDQ R14,R15
146 MOVQ 24(SP),R14
|
| D | freeze_amd64.s | 23 MOVQ R14,24(SP)
87 MOVQ 24(SP),R14
|
| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 126 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
127 ; ALL: sc $[[R14]], 0($[[R2]])
128 ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
129 ; MICROMIPS: beqzc $[[R14]], $[[BB0]]
166 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
167 ; ALL: sc $[[R14]], 0($[[R2]])
168 ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
169 ; MICROMIPS: beqzc $[[R14]], $[[BB0]]
207 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
208 ; ALL: sc $[[R14]], 0($[[R2]])
[all …]
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
|
| D | MSP430RegisterInfo.td | 63 def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
|
| D | MSP430RegisterInfo.cpp | 55 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
61 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
|
| /external/libunwind/src/x86_64/ |
| D | init.h | 63 c->dwarf.loc[R14] = REG_INIT_LOC(c, r14, R14); in common_init()
|
| D | Gget_save_loc.c | 45 case UNW_X86_64_R14: loc = c->dwarf.loc[R14]; break; in unw_get_save_loc()
|
| D | unwind_i.h | 53 #define R14 14 macro
|
| D | Gregs.c | 119 case UNW_X86_64_R14: loc = c->dwarf.loc[R14]; break; in tdep_access_reg()
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 59 def R14 : AVRReg<14, "r14">, DwarfRegNum<[14]>;
99 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
|
| /external/strace/linux/x86_64/ |
| D | userent.h | 2 XLAT(8*R14),
|
| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| D | ptrace-abi.h | 33 #define R14 8 macro
|
| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 146 SUB R14,R9,R3 @// rgb offset in pixels
432 ADD R2,R8,R14,LSL #2 @// rgb = rgb_next + offset
441 ADD R8,R8,R14,LSL #2 @// rgb_next_row = rgb + width + offset
|
| /external/valgrind/coregrind/m_sigframe/ |
| D | sigframe-amd64-darwin.c | 99 SC2(__r14,R14); in synthesize_ucontext()
127 SC2(R14,__r14); in restore_from_ucontext()
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 690 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
727 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
763 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
799 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
800 return X86::R14; in getX86SubSuperRegisterOrZero()
|
| D | X86CallingConv.td | 213 RAX, R10, R11, R13, R14, R15]>>
341 RAX, R10, R11, R13, R14]>>
429 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
802 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
807 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
827 R11, R12, R13, R14, R15, RBP,
843 R13, R14, R15,
847 R12, R13, R14, R15,
858 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
|
| /external/autotest/site_utils/autoupdate/ |
| D | release_config.ini | 14 branch_points: R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22,
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 185 ENTRY(R14) \
203 ENTRY(R14) \
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 61 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, in getCallerSavedRegs()
|
| /external/valgrind/VEX/auxprogs/ |
| D | genoffsets.c | 118 GENOFFSET(AMD64,amd64,R14); in foo()
161 GENOFFSET(ARM,arm,R14); in foo()
|
| /external/google-breakpad/src/common/android/ |
| D | breakpad_getcontext_unittest.cc | 127 CHECK_REG(R14); in TEST()
|