1; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS 2; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS 3; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS 4; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS 5; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS 6; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS 7; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS 8; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS 9 10; Keep one big-endian check so that we don't reduce testing, but don't add more 11; since endianness doesn't affect the body of the atomic operations. 12; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB -check-prefix=NOT-MICROMIPS 13 14@x = common global i32 0, align 4 15 16define i32 @AtomicLoadAdd32(i32 signext %incr) nounwind { 17entry: 18 %0 = atomicrmw add i32* @x, i32 %incr monotonic 19 ret i32 %0 20 21; ALL-LABEL: AtomicLoadAdd32: 22 23; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) 24; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( 25 26; ALL: $[[BB0:[A-Z_0-9]+]]: 27; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) 28; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4 29; ALL: sc $[[R2]], 0($[[R0]]) 30; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] 31; MICROMIPS: beqzc $[[R2]], $[[BB0]] 32} 33 34define i32 @AtomicLoadNand32(i32 signext %incr) nounwind { 35entry: 36 %0 = atomicrmw nand i32* @x, i32 %incr monotonic 37 ret i32 %0 38 39; ALL-LABEL: AtomicLoadNand32: 40 41; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) 42; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( 43 44; ALL: $[[BB0:[A-Z_0-9]+]]: 45; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) 46; ALL: and $[[R3:[0-9]+]], $[[R1]], $4 47; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]] 48; ALL: sc $[[R2]], 0($[[R0]]) 49; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] 50; MICROMIPS: beqzc $[[R2]], $[[BB0]] 51} 52 53define i32 @AtomicSwap32(i32 signext %newval) nounwind { 54entry: 55 %newval.addr = alloca i32, align 4 56 store i32 %newval, i32* %newval.addr, align 4 57 %tmp = load i32, i32* %newval.addr, align 4 58 %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic 59 ret i32 %0 60 61; ALL-LABEL: AtomicSwap32: 62 63; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) 64; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x) 65 66; ALL: $[[BB0:[A-Z_0-9]+]]: 67; ALL: ll ${{[0-9]+}}, 0($[[R0]]) 68; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) 69; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] 70; MICROMIPS: beqzc $[[R2]], $[[BB0]] 71} 72 73define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind { 74entry: 75 %newval.addr = alloca i32, align 4 76 store i32 %newval, i32* %newval.addr, align 4 77 %tmp = load i32, i32* %newval.addr, align 4 78 %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic monotonic 79 %1 = extractvalue { i32, i1 } %0, 0 80 ret i32 %1 81 82; ALL-LABEL: AtomicCmpSwap32: 83 84; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) 85; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( 86 87; ALL: $[[BB0:[A-Z_0-9]+]]: 88; ALL: ll $2, 0($[[R0]]) 89; ALL: bne $2, $4, $[[BB1:[A-Z_0-9]+]] 90; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) 91; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] 92; MICROMIPS: beqzc $[[R2]], $[[BB0]] 93; ALL: $[[BB1]]: 94} 95 96 97 98@y = common global i8 0, align 1 99 100define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { 101entry: 102 %0 = atomicrmw add i8* @y, i8 %incr monotonic 103 ret i8 %0 104 105; ALL-LABEL: AtomicLoadAdd8: 106 107; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y) 108; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)( 109 110; ALL: addiu $[[R1:[0-9]+]], $zero, -4 111; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 112; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3 113; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 114; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 115; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 116; ALL: ori $[[R6:[0-9]+]], $zero, 255 117; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 118; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] 119; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] 120 121; ALL: $[[BB0:[A-Z_0-9]+]]: 122; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) 123; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] 124; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] 125; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] 126; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] 127; ALL: sc $[[R14]], 0($[[R2]]) 128; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] 129; MICROMIPS: beqzc $[[R14]], $[[BB0]] 130 131; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] 132; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] 133 134; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 135; NO-SEB-SEH: sra $2, $[[R17]], 24 136 137; HAS-SEB-SEH: seb $2, $[[R16]] 138} 139 140define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { 141entry: 142 %0 = atomicrmw sub i8* @y, i8 %incr monotonic 143 ret i8 %0 144 145; ALL-LABEL: AtomicLoadSub8: 146 147; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y) 148; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)( 149 150; ALL: addiu $[[R1:[0-9]+]], $zero, -4 151; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 152; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3 153; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 154; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 155; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 156; ALL: ori $[[R6:[0-9]+]], $zero, 255 157; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 158; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] 159; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] 160 161; ALL: $[[BB0:[A-Z_0-9]+]]: 162; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) 163; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]] 164; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] 165; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] 166; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] 167; ALL: sc $[[R14]], 0($[[R2]]) 168; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] 169; MICROMIPS: beqzc $[[R14]], $[[BB0]] 170 171; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] 172; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] 173 174; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 175; NO-SEB-SEH: sra $2, $[[R17]], 24 176 177; HAS-SEB-SEH:seb $2, $[[R16]] 178} 179 180define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { 181entry: 182 %0 = atomicrmw nand i8* @y, i8 %incr monotonic 183 ret i8 %0 184 185; ALL-LABEL: AtomicLoadNand8: 186 187; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y) 188; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)( 189 190; ALL: addiu $[[R1:[0-9]+]], $zero, -4 191; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 192; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3 193; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 194; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 195; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 196; ALL: ori $[[R6:[0-9]+]], $zero, 255 197; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 198; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] 199; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] 200 201; ALL: $[[BB0:[A-Z_0-9]+]]: 202; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) 203; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]] 204; ALL: nor $[[R11:[0-9]+]], $zero, $[[R18]] 205; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] 206; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] 207; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] 208; ALL: sc $[[R14]], 0($[[R2]]) 209; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] 210; MICROMIPS: beqzc $[[R14]], $[[BB0]] 211 212; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] 213; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] 214 215; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 216; NO-SEB-SEH: sra $2, $[[R17]], 24 217 218; HAS-SEB-SEH: seb $2, $[[R16]] 219} 220 221define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { 222entry: 223 %0 = atomicrmw xchg i8* @y, i8 %newval monotonic 224 ret i8 %0 225 226; ALL-LABEL: AtomicSwap8: 227 228; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y) 229; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)( 230 231; ALL: addiu $[[R1:[0-9]+]], $zero, -4 232; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 233; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3 234; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 235; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 236; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 237; ALL: ori $[[R6:[0-9]+]], $zero, 255 238; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 239; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] 240; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] 241 242; ALL: $[[BB0:[A-Z_0-9]+]]: 243; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) 244; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]] 245; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] 246; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]] 247; ALL: sc $[[R14]], 0($[[R2]]) 248; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] 249; MICROMIPS: beqzc $[[R14]], $[[BB0]] 250 251; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] 252; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] 253 254; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 255; NO-SEB-SEH: sra $2, $[[R17]], 24 256 257; HAS-SEB-SEH: seb $2, $[[R16]] 258 259} 260 261define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind { 262entry: 263 %pair0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic monotonic 264 %0 = extractvalue { i8, i1 } %pair0, 0 265 ret i8 %0 266 267; ALL-LABEL: AtomicCmpSwap8: 268 269; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y) 270; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)( 271 272; ALL: addiu $[[R1:[0-9]+]], $zero, -4 273; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 274; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3 275; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 276; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 277; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 278; ALL: ori $[[R6:[0-9]+]], $zero, 255 279; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 280; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] 281; ALL: andi $[[R9:[0-9]+]], $4, 255 282; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]] 283; ALL: andi $[[R11:[0-9]+]], $5, 255 284; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]] 285 286; ALL: $[[BB0:[A-Z_0-9]+]]: 287; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) 288; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] 289; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] 290 291; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] 292; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] 293; ALL: sc $[[R16]], 0($[[R2]]) 294; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] 295; MICROMIPS: beqzc $[[R16]], $[[BB0]] 296 297; ALL: $[[BB1]]: 298; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] 299 300; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24 301; NO-SEB-SEH: sra $2, $[[R18]], 24 302 303; HAS-SEB-SEH: seb $2, $[[R17]] 304} 305 306define i1 @AtomicCmpSwapRes8(i8* %ptr, i8 signext %oldval, i8 signext %newval) nounwind { 307entry: 308 %0 = cmpxchg i8* %ptr, i8 %oldval, i8 %newval monotonic monotonic 309 %1 = extractvalue { i8, i1 } %0, 1 310 ret i1 %1 311; ALL-LABEL: AtomicCmpSwapRes8 312 313; ALL: addiu $[[R1:[0-9]+]], $zero, -4 314; ALL: and $[[R2:[0-9]+]], $4, $[[R1]] 315; ALL: andi $[[R3:[0-9]+]], $4, 3 316; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 317; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 318; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 319; ALL: ori $[[R6:[0-9]+]], $zero, 255 320; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 321; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] 322; ALL: andi $[[R9:[0-9]+]], $5, 255 323; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]] 324; ALL: andi $[[R11:[0-9]+]], $6, 255 325; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]] 326 327; ALL: $[[BB0:[A-Z_0-9]+]]: 328; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) 329; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] 330; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] 331 332; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] 333; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] 334; ALL: sc $[[R16]], 0($[[R2]]) 335; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] 336; MICROMIPS: beqzc $[[R16]], $[[BB0]] 337 338; ALL: $[[BB1]]: 339; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] 340 341; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24 342; NO-SEB-SEH: sra $[[R19:[0-9]+]], $[[R18]], 24 343 344; HAS-SEB-SEH: seb $[[R19:[0-9]+]], $[[R17]] 345 346; ALL: xor $[[R20:[0-9]+]], $[[R19]], $5 347; ALL: sltiu $2, $[[R20]], 1 348} 349 350; Check one i16 so that we cover the seh sign extend 351@z = common global i16 0, align 1 352 353define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { 354entry: 355 %0 = atomicrmw add i16* @z, i16 %incr monotonic 356 ret i16 %0 357 358; ALL-LABEL: AtomicLoadAdd16: 359 360; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(z) 361; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(z)( 362 363; ALL: addiu $[[R1:[0-9]+]], $zero, -4 364; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 365; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3 366; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 2 367; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 368; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 369; ALL: ori $[[R6:[0-9]+]], $zero, 65535 370; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 371; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] 372; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] 373 374; ALL: $[[BB0:[A-Z_0-9]+]]: 375; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) 376; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] 377; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] 378; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] 379; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] 380; ALL: sc $[[R14]], 0($[[R2]]) 381; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] 382; MICROMIPS: beqzc $[[R14]], $[[BB0]] 383 384; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] 385; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] 386 387; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 16 388; NO-SEB-SEH: sra $2, $[[R17]], 16 389 390; MIPS32R2: seh $2, $[[R16]] 391} 392 393 394@countsint = common global i32 0, align 4 395 396define i32 @CheckSync(i32 signext %v) nounwind noinline { 397entry: 398 %0 = atomicrmw add i32* @countsint, i32 %v seq_cst 399 ret i32 %0 400 401; ALL-LABEL: CheckSync: 402 403; ALL: sync 404; ALL: ll 405; ALL: sc 406; ALL: beq 407; ALL: sync 408} 409 410; make sure that this assertion in 411; TwoAddressInstructionPass::TryInstructionTransform does not fail: 412; 413; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) && 414; 415; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an 416; operand of an atomic instruction with register $zero. 417@a = external global i32 418 419define i32 @zeroreg() nounwind { 420entry: 421 %pair0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst seq_cst 422 %0 = extractvalue { i32, i1 } %pair0, 0 423 %1 = icmp eq i32 %0, 1 424 %conv = zext i1 %1 to i32 425 ret i32 %conv 426} 427 428; Check that MIPS32R6 has the correct offset range. 429; FIXME: At the moment, we don't seem to do addr+offset for any atomic load/store. 430define i32 @AtomicLoadAdd32_OffGt9Bit(i32 signext %incr) nounwind { 431entry: 432 %0 = atomicrmw add i32* getelementptr(i32, i32* @x, i32 256), i32 %incr monotonic 433 ret i32 %0 434 435; ALL-LABEL: AtomicLoadAdd32_OffGt9Bit: 436 437; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) 438; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( 439 440; ALL: addiu $[[PTR:[0-9]+]], $[[R0]], 1024 441; ALL: $[[BB0:[A-Z_0-9]+]]: 442; ALL: ll $[[R1:[0-9]+]], 0($[[PTR]]) 443; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4 444; ALL: sc $[[R2]], 0($[[PTR]]) 445; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] 446; MICROMIPS: beqzc $[[R2]], $[[BB0]] 447} 448