| /external/boringssl/src/ssl/test/runner/curve25519/ |
| D | cswap_amd64.s | 20 MOVQ SI,R9
22 CMOVQEQ R9,DX
23 MOVQ CX,R9
25 CMOVQEQ R9,R8
34 MOVQ SI,R9
36 CMOVQEQ R9,DX
37 MOVQ CX,R9
39 CMOVQEQ R9,R8
48 MOVQ SI,R9
50 CMOVQEQ R9,DX
[all …]
|
| D | ladderstep_amd64.s | 31 MOVQ 72(DI),R9
36 MOVQ R9,R13
46 ADDQ 112(DI),R9
56 MOVQ R9,88(SP)
70 MOVQ DX,R9
118 ADCQ DX,R9
123 ADCQ DX,R9
137 SHLQ $13,R9:R8
142 ADDQ R9,R10
159 MOVQ CX,R9
[all …]
|
| D | square_amd64.s | 35 MOVQ AX,R9
83 ADDQ AX,R9
88 ADDQ AX,R9
103 SHLQ $13,R10:R9
104 ANDQ SI,R9
105 ADDQ R8,R9
119 ADDQ R9,DX
125 MOVQ DX,R9
128 ANDQ SI,R9
140 MOVQ R9,16(DI)
|
| D | freeze_amd64.s | 31 MOVQ 32(DI),R9
52 ADDQ R12,R9
53 MOVQ R9,R12
55 ANDQ AX,R9
69 CMPQ AX,R9
78 SUBQ AX,R9
83 MOVQ R9,32(DI)
|
| D | mul_amd64.s | 36 MOVQ DX,R9
42 ADCQ DX,R9
46 ADCQ DX,R9
83 ADCQ DX,R9
100 ADCQ DX,R9
139 SHLQ $13,R9:R8
143 ADDQ R9,R10
162 MOVQ DX,R9
168 ANDQ SI,R9
178 MOVQ R9,16(DI)
|
| /external/boringssl/src/ssl/test/runner/poly1305/ |
| D | poly1305_arm.s | 25 MOVW R2>>26, R9
29 ORR R3<<6, R9, R9
34 AND R9, R3, R3
61 MOVM.DB.W [R4, R5, R6, R7, R8, R9, g, R11, R14], (R13)
74 MOVM.IA (R0), [R0-R9]
111 ADD R4, R9, R9
123 MULALU R0, R9, (R11, g)
124 MULALU R4, R9, (R14, R12)
139 MULALU R3, R9, (R11, g)
140 MULALU R2, R9, (R14, R12)
[all …]
|
| D | poly1305_amd64.s | 18 MOVQ $31,R9
19 NOTQ R9
20 ANDQ R9,SP
32 MOVL 4(CX),R9
42 ANDL $0X0FFFFFFC,R9
46 MOVL R9,112(SP)
79 MOVL 0(SI),R9
83 MOVL R9,104(SP)
104 MOVL 0(SI),R9
108 MOVL R9,104(SP)
[all …]
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/warp/detail/ |
| D | reduce.hpp | 138 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9>
140 … const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in loadToSmem()
156 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9,
159 const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in merge()
177 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9,
179 …__device__ __forceinline__ void mergeShfl(const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in mergeShfl()
184 …For<0, tuple_size<tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9> >::value>::mergeShfl(val, delta, w… in mergeShfl()
|
| /external/opencv3/modules/core/include/opencv2/core/cuda/detail/ |
| D | reduce.hpp | 138 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9>
140 … const thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in loadToSmem()
146 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9>
148 … const thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in loadFromSmem()
167 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9,
170 … const thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in merge()
177 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9,
179 …__ __forceinline__ void mergeShfl(const thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in mergeShfl()
184 …For<0, thrust::tuple_size<thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9> >::value>::mergeSh… in mergeShfl()
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/block/detail/ |
| D | reduce.hpp | 158 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9>
160 … const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in loadToSmem()
167 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9>
169 … const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in loadFromSmem()
185 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9,
188 const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in merge()
206 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9,
208 …__device__ __forceinline__ void mergeShfl(const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in mergeShfl()
213 …For<0, tuple_size<tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9> >::value>::mergeShfl(val, delta, w… in mergeShfl()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.cpp | 44 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
49 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
54 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
60 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
|
| D | MSP430RegisterInfo.td | 58 def R9 : MSP430RegWithSubregs<9, "r9", [R9B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
|
| /external/pdfium/testing/resources/ |
| D | bug_547706.in | 18 /R9 scn
26 << /R9 7 0 R >>
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
|
| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 119 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
123 ; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
159 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
163 ; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
199 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
203 ; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
240 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
244 ; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]
281 ; ALL: andi $[[R9:[0-9]+]], $4, 255
282 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
[all …]
|
| /external/valgrind/VEX/orig_ppc32/ |
| D | return0.orig | 100 43: PUTL t30, R9
147 76: GETL R9, t58
152 79: GETL R9, t60
154 81: PUTL t60, R9
172 1: GETL R9, t2
177 4: GETL R9, t4
179 6: PUTL t4, R9
315 52: PUTL t40, R9
319 54: GETL R9, t42
326 59: GETL R9, t46
[all …]
|
| D | date.orig | 100 43: PUTL t30, R9
147 76: GETL R9, t58
152 79: GETL R9, t60
154 81: PUTL t60, R9
172 1: GETL R9, t2
177 4: GETL R9, t4
179 6: PUTL t4, R9
315 52: PUTL t40, R9
319 54: GETL R9, t42
326 59: GETL R9, t46
[all …]
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFRegisterInfo.td | 31 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
37 R6, R7, R8, R9, // callee saved
|
| D | BPFFrameLowering.cpp | 39 SavedRegs.reset(BPF::R9); in determineCalleeSaves()
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/block/ |
| D | reduce.hpp | 70 …name R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9,
73 … const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, in blockReduce()
79 const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>&, in blockReduce()
|
| /external/libunwind/src/x86_64/ |
| D | init.h | 58 c->dwarf.loc[R9] = REG_INIT_LOC(c, r9, R9); in common_init()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.td | 106 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
210 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
217 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
221 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
223 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
226 (sub CSR_AAPCS_ThisReturn, R9))>;
|
| D | ARMBaseRegisterInfo.h | 41 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
52 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 54 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
102 def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>;
124 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
|
| /external/strace/linux/x86_64/ |
| D | userent.h | 9 XLAT(8*R9),
|