| /external/v8/src/arm64/ |
| D | constants-arm64.h | 916 REV16 = DataProcessing1SourceFixed | 0x00000400, enumerator
917 REV16_w = REV16,
918 REV16_x = REV16 | SixtyFourBits,
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| D | disasm-arm64.cc | 579 FORMAT(REV16, "rev16"); in VisitDataProcessing1Source()
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| D | assembler-arm64.cc | 1546 DataProcessing1Source(rd, rn, REV16); in rev16()
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 342 # REV/REV16/REVSH
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| D | thumb2.txt | 1460 # REV16
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| D | basic-arm-instructions.txt | 1201 # REV/REV16/REVSH
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 107 REV16, enumerator
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| D | AArch64SchedCyclone.td | 147 // CLS,CLZ,RBIT,REV,REV16,REV32
497 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
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| D | AArch64ISelLowering.cpp | 884 case AArch64ISD::REV16: return "AArch64ISD::REV16"; in getTargetNodeName()
5356 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
5539 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
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| D | AArch64InstrInfo.td | 214 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
2795 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 1020 REV16 = DataProcessing1SourceFixed | 0x00000400, enumerator
1021 REV16_w = REV16,
1022 REV16_x = REV16 | SixtyFourBits,
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| D | disasm-a64.cc | 592 FORMAT(REV16, "rev16"); in VisitDataProcessing1Source()
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| D | assembler-a64.cc | 1418 DataProcessing1Source(rd, rn, REV16); in rev16()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-rev.ll | 39 ; 64-bit REV16 is *not* a swap then a 16-bit rotation:
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 472 @ REV/REV16/REVSH
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| D | basic-thumb2-instructions.s | 1948 @ REV16
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| D | basic-arm-instructions.s | 1855 @ REV/REV16/REVSH
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| D | v8_IT_manual.s | 572 @ REV16, encoding T1
576 @ REV16, encoding T2 (32-bit)
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 129 // CLZ,RBIT,REV,REV16,REVSH,PKH
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| D | ARMInstrInfo.td | 4209 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4216 (REV16 (LDRH addrmode3:$addr))>;
4218 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
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| D | ARMInstrThumb2.td | 4570 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
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| /external/vixl/doc/ |
| D | supported-instructions.md | 961 ### REV16 ### subsection
2882 ### REV16 ### subsection
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| /external/valgrind/none/tests/arm64/ |
| D | integer.stdout.exp | 1816 REV16
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| /external/valgrind/none/tests/arm/ |
| D | v6intARM.stdout.exp | 820 ------------ REV16 ------------
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| D | v6intThumb.stdout.exp | 16718 (T1) REV16 Rd, Rm ------------
16737 (T2) REV16 Rd, Rm ------------
|