| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 142 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
145 MFI->hasPatchPoint() || RegInfo->needsStackRealignment(MF)); in hasFP()
284 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in emitPrologue() local
355 const bool NeedsRealignment = RegInfo->needsStackRealignment(MF); in emitPrologue()
399 if (RegInfo->hasBasePointer(MF)) { in emitPrologue()
400 TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP, in emitPrologue()
407 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
476 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true); in emitPrologue()
484 unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true); in emitPrologue()
543 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in emitEpilogue() local
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| D | AArch64CleanupLocalDynamicTLSPass.cpp | 116 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in setRegister() local
117 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 77 const MipsRegisterInfo &RegInfo; member in __anonbe7f5cdf0111::ExpandPseudo
85 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo()
156 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond()
160 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
171 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond()
177 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
189 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
193 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
194 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
198 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
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| D | MipsSERegisterInfo.cpp | 116 const MipsRegisterInfo *RegInfo = in eliminateFI() local
143 else if (RegInfo->needsStackRealignment(MF)) { in eliminateFI()
184 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in eliminateFI() local
185 unsigned Reg = RegInfo.createVirtualRegister(PtrRC); in eliminateFI()
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| D | MipsISelLowering.cpp | 1062 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitAtomicBinary() local
1093 unsigned StoreVal = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
1094 unsigned AndRes = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
1095 unsigned Success = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
1160 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitSignExtendToI32InReg() local
1162 unsigned ScrReg = RegInfo.createVirtualRegister(RC); in emitSignExtendToI32InReg()
1180 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitAtomicBinaryPartword() local
1189 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1190 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1191 unsigned Mask = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
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| D | Mips16ISelDAGToDAG.cpp | 74 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg() local
80 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
81 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
82 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| D | MipsSEISelLowering.cpp | 2925 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitBPOSGE32() local
2954 unsigned VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
2960 unsigned VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
2990 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitMSACBranchPseudo() local
3021 unsigned RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3027 unsigned RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3053 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FW() local
3064 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); in emitCOPY_FW()
3071 unsigned Wt = RegInfo.createVirtualRegister( in emitCOPY_FW()
3098 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FD() local
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb1FrameLowering.cpp | 57 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local
76 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
79 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
93 const ThumbRegisterInfo *RegInfo = in emitPrologue() local
108 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
109 unsigned BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
122 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue()
134 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize), in emitPrologue()
267 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
289 if (RegInfo->needsStackRealignment(MF)) in emitPrologue()
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| D | ARMFrameLowering.cpp | 59 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
69 RegInfo->needsStackRealignment(MF) || in hasFP()
299 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); in emitPrologue() local
313 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
648 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { in emitPrologue()
678 if (RegInfo->hasBasePointer(MF)) { in emitPrologue()
681 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
686 RegInfo->getBaseRegister()) in emitPrologue()
701 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in emitEpilogue() local
710 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitEpilogue()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 93 const SparcRegisterInfo &RegInfo = in emitPrologue() local
99 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF); in emitPrologue()
158 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); in emitPrologue()
171 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue()
172 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); in emitPrologue()
234 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
238 RegInfo->needsStackRealignment(MF) || in hasFP()
248 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in getFrameIndexReference() local
266 } else if (RegInfo->needsStackRealignment(MF)) { in getFrameIndexReference()
280 FrameReg = RegInfo->getFrameRegister(MF); in getFrameIndexReference()
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| /external/llvm/lib/Target/X86/ |
| D | X86MachineFunctionInfo.cpp | 20 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( in setRestoreBasePointer() local
22 unsigned SlotSize = RegInfo->getSlotSize(); in setRestoreBasePointer()
24 RegInfo->X86RegisterInfo::getCalleeSavedRegs(MF); in setRestoreBasePointer()
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| D | X86CallFrameOptimization.cpp | 100 const X86RegisterInfo &RegInfo,
257 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
298 if (!RegInfo.isPhysicalRegister(Reg)) in classifyInstruction()
300 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction()
304 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction()
318 const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>( in collectCallInfo() local
363 while ((Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs)) != in collectCallInfo()
409 if (RegInfo.isPhysicalRegister(Reg)) in collectCallInfo()
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| /external/llvm/lib/CodeGen/ |
| D | MachineFunction.cpp | 68 RegInfo = new (Allocator) MachineRegisterInfo(this); in MachineFunction()
70 RegInfo = nullptr; in MachineFunction()
116 if (RegInfo) { in ~MachineFunction()
117 RegInfo->~MachineRegisterInfo(); in ~MachineFunction()
118 Allocator.Deallocate(RegInfo); in ~MachineFunction()
365 if (RegInfo) { in print()
366 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA"); in print()
367 if (!RegInfo->tracksLiveness()) in print()
384 if (RegInfo && !RegInfo->livein_empty()) { in print()
387 I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) { in print()
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| D | MachineInstr.cpp | 179 MachineRegisterInfo *RegInfo = nullptr; in ChangeToRegister() local
183 RegInfo = &MF->getRegInfo(); in ChangeToRegister()
187 if (RegInfo && WasReg) in ChangeToRegister()
188 RegInfo->removeRegOperandFromUseList(this); in ChangeToRegister()
210 if (RegInfo) in ChangeToRegister()
211 RegInfo->addRegOperandToUseList(this); in ChangeToRegister()
1383 const TargetRegisterInfo &RegInfo) { in substituteRegister() argument
1386 ToReg = RegInfo.getSubReg(ToReg, SubIdx); in substituteRegister()
1390 MO.substPhysReg(ToReg, RegInfo); in substituteRegister()
1396 MO.substVirtReg(ToReg, SubIdx, RegInfo); in substituteRegister()
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| D | MIRPrinter.cpp | 79 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
198 const MachineRegisterInfo &RegInfo, in convert() argument
200 MF.IsSSA = RegInfo.isSSA(); in convert()
201 MF.TracksRegLiveness = RegInfo.tracksLiveness(); in convert()
202 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled(); in convert()
205 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { in convert()
210 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in convert()
211 unsigned PreferredReg = RegInfo.getSimpleHint(Reg); in convert()
218 for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) { in convert()
227 const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask(); in convert()
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| D | PrologEpilogInserter.cpp | 302 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo(); in assignCalleeSavedSpillSlots() local
303 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F); in assignCalleeSavedSpillSlots()
314 if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) { in assignCalleeSavedSpillSlots()
329 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
332 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) { in assignCalleeSavedSpillSlots()
620 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); in calculateFrameObjectOffsets() local
623 RegInfo->useFPForScavengingIndex(Fn) && in calculateFrameObjectOffsets()
624 !RegInfo->needsStackRealignment(Fn)); in calculateFrameObjectOffsets()
752 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0)) in calculateFrameObjectOffsets()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.h | 27 const NVPTXRegisterInfo RegInfo; variable
32 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } in getRegisterInfo()
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| D | NVPTXPrologEpilogPass.cpp | 113 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); in calculateFrameObjectOffsets() local
213 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0)) in calculateFrameObjectOffsets()
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| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 338 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initializeRegisterInfo() local
339 assert(RegInfo.isSSA()); in initializeRegisterInfo()
341 RegInfo.leaveSSA(); in initializeRegisterInfo()
342 assert(RegInfo.tracksLiveness()); in initializeRegisterInfo()
344 RegInfo.invalidateLiveness(); in initializeRegisterInfo()
345 RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness); in initializeRegisterInfo()
355 unsigned Reg = RegInfo.createVirtualRegister(RC); in initializeRegisterInfo()
367 RegInfo.setSimpleHint(Reg, PreferredReg); in initializeRegisterInfo()
383 RegInfo.addLiveIn(Reg, VReg); in initializeRegisterInfo()
387 BitVector CalleeSavedRegisterMask(RegInfo.getUsedPhysRegsMask().size()); in initializeRegisterInfo()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1414 typedef DenseMapInfo<unsigned> RegInfo;
1417 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1418 RegInfo::getEmptyKey());
1421 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1422 RegInfo::getTombstoneKey());
1433 return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1434 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZLDCleanup.cpp | 132 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in SetRegister() local
133 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&SystemZ::GR64BitRegClass); in SetRegister()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 438 const PPCRegisterInfo *RegInfo = in determineFrameLayout() local
447 unsigned LR = RegInfo->getRARegister(); in determineFrameLayout()
456 !RegInfo->hasBasePointer(MF)) { // No special alignment. in determineFrameLayout()
525 const PPCRegisterInfo *RegInfo = in replaceFPWithRealFP() local
527 bool HasBP = RegInfo->hasBasePointer(MF); in replaceFPWithRealFP()
528 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; in replaceFPWithRealFP()
624 const PPCRegisterInfo *RegInfo = in emitPrologue() local
669 bool HasBP = RegInfo->hasBasePointer(MF); in emitPrologue()
672 unsigned BPReg = RegInfo->getBaseRegister(MF); in emitPrologue()
990 const PPCRegisterInfo *RegInfo = in emitEpilogue() local
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyPEI.cpp | 318 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo(); in assignCalleeSavedSpillSlots() local
319 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F); in assignCalleeSavedSpillSlots()
330 if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) { in assignCalleeSavedSpillSlots()
345 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
348 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) { in assignCalleeSavedSpillSlots()
636 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); in calculateFrameObjectOffsets() local
639 RegInfo->useFPForScavengingIndex(Fn) && in calculateFrameObjectOffsets()
640 !RegInfo->needsStackRealignment(Fn)); in calculateFrameObjectOffsets()
768 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0)) in calculateFrameObjectOffsets()
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| D | WebAssemblyFrameLowering.cpp | 47 const auto *RegInfo = in hasFP() local
51 RegInfo->needsStackRealignment(MF); in hasFP()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 1038 const TargetRegisterInfo &RegInfo);
1045 const TargetRegisterInfo *RegInfo,
1050 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1056 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1070 const TargetRegisterInfo *RegInfo = nullptr);
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