| /external/llvm/lib/Target/BPF/InstPrinter/ |
| D | BPFInstPrinter.cpp | 68 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
77 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()
78 O << '(' << getRegisterName(RegOp.getReg()) << ')'; in printMemOperand()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 498 unsigned RegOp = OpNum; in PrintAsmOperand() local
504 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
507 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
510 RegOp = OpNum + 1; in PrintAsmOperand()
512 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
514 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfCompileUnit.cpp | 498 const MachineOperand RegOp = DVInsn->getOperand(0); in constructVariableDIEImpl() local
501 MachineLocation Location(RegOp.getReg(), in constructVariableDIEImpl()
504 } else if (RegOp.getReg()) in constructVariableDIEImpl()
505 addVariableAddress(DV, *VariableDie, MachineLocation(RegOp.getReg())); in constructVariableDIEImpl()
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 84 struct RegOp { struct in __anoncbe3518a0111::AMDGPUOperand
95 RegOp Reg;
1177 AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[PrevRegIdx]); in parseOperand() local
1178 RegOp.setModifiers(0); in parseOperand()
1188 AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[Operands.size() - 1]); in parseOperand() local
1189 RegOp.setModifiers(Modifiers); in parseOperand()
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 44 struct RegOp { struct
64 struct RegOp Reg;
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 166 unsigned RegOp, unsigned MemOp, unsigned Flags);
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| D | X86MCInstLower.cpp | 357 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm() local
359 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && in SimplifyShortMoveForm()
369 unsigned Reg = Inst.getOperand(RegOp).getReg(); in SimplifyShortMoveForm()
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| D | X86InstrInfo.cpp | 96 uint16_t RegOp; member
277 Entry.RegOp, Entry.MemOp, in X86InstrInfo()
432 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags); in X86InstrInfo()
865 Entry.RegOp, Entry.MemOp, in X86InstrInfo()
1734 Entry.RegOp, Entry.MemOp, in X86InstrInfo()
1971 Entry.RegOp, Entry.MemOp, in X86InstrInfo()
2020 Entry.RegOp, Entry.MemOp, in X86InstrInfo()
2029 unsigned RegOp, unsigned MemOp, unsigned Flags) { in AddTableEntry() argument
2031 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); in AddTableEntry()
2032 R2MTable[RegOp] = std::make_pair(MemOp, Flags); in AddTableEntry()
[all …]
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 86 struct RegOp { struct in __anon268cb60c0111::SystemZOperand
113 RegOp Reg;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 364 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; in PrintAsmOperand() local
365 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
367 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 183 struct RegOp { struct in __anon8582bd000111::SparcOperand
200 struct RegOp Reg;
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 175 struct RegOp { struct in __anonbb8448a00211::AArch64Operand
250 struct RegOp Reg;
4035 AArch64Operand &RegOp = static_cast<AArch64Operand &>(*Operands[1]); in MatchAndEmitInstruction() local
4037 if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) { in MatchAndEmitInstruction()
4040 RegOp.getReg()) in MatchAndEmitInstruction()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 1259 if (const auto *RegOp = dyn_cast<RegisterMaskSDNode>(Op.getNode())) in getNodeRegMask() local
1260 return RegOp->getRegMask(); in getNodeRegMask()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 468 struct RegOp { struct in __anone97f5c0e0311::ARMOperand
552 struct RegOp Reg;
4624 unsigned RegOp = 4; in cvtThumbMultiply() local
4628 RegOp = 5; in cvtThumbMultiply()
4629 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV4.td | 1575 bits<5> RegOp; // Non-New-Value Operand
1583 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1591 let Inst{12-8} = RegOp;
|