Searched refs:SCVTF (Results 1 – 9 of 9) sorted by relevance
/external/v8/src/arm64/ |
D | constants-arm64.h | 1168 SCVTF = FPIntegerConvertFixed | 0x00020000, enumerator 1169 SCVTF_sw = SCVTF, 1170 SCVTF_sx = SCVTF | SixtyFourBits, 1171 SCVTF_dw = SCVTF | FP64, 1172 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
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D | assembler-arm64.cc | 2024 Emit(SF(rn) | FPType(fd) | SCVTF | Rn(rn) | Rd(fd)); in scvtf()
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-basic-a64-undefined.txt | 26 # SCVTF on fixed point W-registers is undefined if scale<5> == 0.
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/external/vixl/src/vixl/a64/ |
D | constants-a64.h | 1278 SCVTF = FPIntegerConvertFixed | 0x00020000, enumerator 1279 SCVTF_sw = SCVTF, 1280 SCVTF_sx = SCVTF | SixtyFourBits, 1281 SCVTF_dw = SCVTF | FP64, 1282 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
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D | assembler-a64.cc | 2966 Emit(SF(rn) | FPType(vd) | SCVTF | Rn(rn) | Rd(vd)); in scvtf()
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/external/pcre/dist/sljit/ |
D | sljitNativeARM_64.c | 108 #define SCVTF 0x9e620000 macro 1647 FAIL_IF(push_inst(compiler, (SCVTF ^ inv_bits) | VD(dst_r) | RN(src))); in sljit_emit_fop1_convd_fromw()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 2478 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>; 2801 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>; 3283 defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>; 4583 defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">; 4657 defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf", 4828 // SCVTF GPR -> FPR is 9 cycles. 4829 // SCVTF FPR -> FPR is 4 cyclces. 4831 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR 4882 // SCVTF on floating point registers (both source and destination
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D | AArch64SchedCyclone.td | 572 // SCVTF,UCVTF V,V
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/external/vixl/doc/ |
D | supported-instructions.md | 3056 ### SCVTF ### subsection 3063 ### SCVTF ### subsection
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