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Searched refs:SU (Results 1 – 25 of 109) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { in isResourceAvailable() argument
44 if (!SU || !SU->getInstr()) in isResourceAvailable()
49 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
51 if (!ResourcesModel->canReserveResources(SU->getInstr())) in isResourceAvailable()
75 if (I->getSUnit() == SU) in isResourceAvailable()
83 bool VLIWResourceModel::reserveResources(SUnit *SU) { in reserveResources() argument
86 if (!SU) { in reserveResources()
94 if (!isResourceAvailable(SU)) { in reserveResources()
101 switch (SU->getInstr()->getOpcode()) { in reserveResources()
103 ResourcesModel->reserveResources(SU->getInstr()); in reserveResources()
[all …]
DHexagonMachineScheduler.h87 bool isResourceAvailable(SUnit *SU);
88 bool reserveResources(SUnit *SU);
115 SUnit *SU; member
123 SchedCandidate(): SU(nullptr), SCost(0) {} in SchedCandidate()
176 bool checkHazard(SUnit *SU);
178 void releaseNode(SUnit *SU, unsigned ReadyCycle);
182 void bumpNode(SUnit *SU);
186 void removeReady(SUnit *SU);
214 void schedNode(SUnit *SU, bool IsTopNode) override;
216 void releaseTopNode(SUnit *SU) override;
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/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberRCValPredInSU()
107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU() argument
110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberRCValSuccInSU()
145 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU() argument
147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberCtrlDepsInSU()
155 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU() argument
157 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberCtrlPredInSU()
173 SUnit *SU = &(*SUnits)[i]; in initNodes() local
174 initNumRegDefsLeft(SU); in initNodes()
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DScheduleDAGRRList.cpp186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
187 return Topo.IsReachable(SU, TargetSU); in IsReachable()
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
193 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
199 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
200 Topo.AddPred(SU, D.getSUnit()); in AddPred()
201 SU->addPred(D); in AddPred()
207 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
208 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
209 SU->removePred(D); in RemovePred()
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DScheduleDAGSDNodes.cpp78 SUnit *SU = &SUnits.back(); in newSUnit() local
83 SU->SchedulingPref = Sched::None; in newSUnit()
85 SU->SchedulingPref = TLI.getSchedulingPreference(N); in newSUnit()
86 return SU; in newSUnit()
90 SUnit *SU = newSUnit(Old->getNode()); in Clone() local
91 SU->OrigNode = Old->OrigNode; in Clone()
92 SU->Latency = Old->Latency; in Clone()
93 SU->isVRegCycle = Old->isVRegCycle; in Clone()
94 SU->isCall = Old->isCall; in Clone()
95 SU->isCallOp = Old->isCallOp; in Clone()
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DScheduleDAGFast.cpp88 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
89 SU->addPred(D); in AddPred()
94 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
95 SU->removePred(D); in RemovePred()
99 void ReleasePred(SUnit *SU, SDep *PredEdge);
100 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
140 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { in ReleasePred() argument
161 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigned CurCycle) { in ReleasePredecessors() argument
163 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in ReleasePredecessors()
165 ReleasePred(SU, &*I); in ReleasePredecessors()
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DScheduleDAGVLIW.cpp87 void releaseSucc(SUnit *SU, const SDep &D);
88 void releaseSuccessors(SUnit *SU);
89 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
116 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { in releaseSucc() argument
131 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); in releaseSucc()
140 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
142 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in releaseSuccessors()
147 releaseSucc(SU, *I); in releaseSuccessors()
154 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { in scheduleNodeTopDown() argument
156 DEBUG(SU->dump(this)); in scheduleNodeTopDown()
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DScheduleDAGSDNodes.h91 void InitNumRegDefsLeft(SUnit *SU);
95 virtual void computeLatency(SUnit *SU);
115 void dumpNode(const SUnit *SU) const override;
119 std::string getGraphNodeLabel(const SUnit *SU) const override;
135 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
175 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
/external/llvm/lib/CodeGen/
DMachineScheduler.cpp542 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc() argument
561 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
562 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
570 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
571 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in releaseSuccessors()
573 releaseSucc(SU, &*I); in releaseSuccessors()
581 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { in releasePred() argument
600 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) in releasePred()
601 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency(); in releasePred()
609 void ScheduleDAGMI::releasePredecessors(SUnit *SU) { in releasePredecessors() argument
[all …]
DScheduleDAGInstrs.cpp247 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
248 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
259 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
260 if (UseSU == SU) in addPhysRegDataDeps()
269 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
273 SU->hasPhysRegDefs = true; in addPhysRegDataDeps()
274 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
278 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
281 ST.adjustSchedDependency(SU, UseSU, Dep); in addPhysRegDataDeps()
290 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDeps() argument
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DLatencyPriorityQueue.cpp56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { in getSingleUnscheduledPred() argument
58 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in getSingleUnscheduledPred()
73 void LatencyPriorityQueue::push(SUnit *SU) { in push() argument
77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in push()
79 if (getSingleUnscheduledPred(I->getSUnit()) == SU) in push()
82 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; in push()
84 Queue.push_back(SU); in push()
92 void LatencyPriorityQueue::scheduledNode(SUnit *SU) { in scheduledNode() argument
93 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in scheduledNode()
105 void LatencyPriorityQueue::AdjustPriorityOfUnscheduledPreds(SUnit *SU) { in AdjustPriorityOfUnscheduledPreds() argument
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DScheduleDAG.cpp183 SUnit *SU = WorkList.pop_back_val(); in setDepthDirty() local
184 SU->isDepthCurrent = false; in setDepthDirty()
185 for (SUnit::const_succ_iterator I = SU->Succs.begin(), in setDepthDirty()
186 E = SU->Succs.end(); I != E; ++I) { in setDepthDirty()
199 SUnit *SU = WorkList.pop_back_val(); in setHeightDirty() local
200 SU->isHeightCurrent = false; in setHeightDirty()
201 for (SUnit::const_pred_iterator I = SU->Preds.begin(), in setHeightDirty()
202 E = SU->Preds.end(); I != E; ++I) { in setHeightDirty()
471 SUnit *SU = &SUnits[i]; in InitDAGTopologicalSorting() local
472 int NodeNum = SU->NodeNum; in InitDAGTopologicalSorting()
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DPostRASchedulerList.cpp179 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
180 void ReleaseSuccessors(SUnit *SU);
181 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
245 if (SUnit *SU = Sequence[i]) in dumpSchedule() local
246 SU->dump(this); in dumpSchedule()
403 for (const SUnit &SU : SUnits) { in schedule()
404 SU.dumpAll(this); in schedule()
438 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) { in ReleaseSucc() argument
473 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) { in ReleaseSuccessors() argument
474 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in ReleaseSuccessors()
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/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp58 SUnit *SU = nullptr; in pickNode() local
98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || in pickNode()
101 SU = pickAlu(); in pickNode()
102 if (!SU && !PhysicalRegCopy.empty()) { in pickNode()
103 SU = PhysicalRegCopy.front(); in pickNode()
106 if (SU) { in pickNode()
113 if (!SU) { in pickNode()
115 SU = pickOther(IDFetch); in pickNode()
116 if (SU) in pickNode()
121 if (!SU) { in pickNode()
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DR600MachineScheduler.h78 void schedNode(SUnit *SU, bool IsTopNode) override;
79 void releaseTopNode(SUnit *SU) override;
80 void releaseBottomNode(SUnit *SU) override;
86 int getInstKind(SUnit *SU);
88 AluKind getAluKind(SUnit *SU) const;
/external/llvm/test/CodeGen/ARM/
D2012-06-12-SchedMemLatency.ll8 ; CHECK: SU(2){{.*}}STR{{.*}}Volatile
9 ; CHECK-NOT: ch SU
10 ; CHECK: ch SU(3): Latency=1
11 ; CHECK-NOT: ch SU
12 ; CHECK: SU(3){{.*}}LDR{{.*}}Volatile
13 ; CHECK-NOT: ch SU
14 ; CHECK: ch SU(2): Latency=1
15 ; CHECK-NOT: ch SU
18 ; CHECK: SU(2){{.*}}STR{{.*}}
19 ; CHECK-NOT: ch SU
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/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp26 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) { in isLoadAfterStore() argument
28 if (isBCTRAfterSet(SU)) in isLoadAfterStore()
31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
40 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) { in isLoadAfterStore()
41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
45 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier()) in isLoadAfterStore()
49 if (SU->Preds[i].getSUnit() == CurGroup[j]) in isLoadAfterStore()
56 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) { in isBCTRAfterSet() argument
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
66 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) { in isBCTRAfterSet()
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DPPCHazardRecognizers.h31 bool isLoadAfterStore(SUnit *SU);
32 bool isBCTRAfterSet(SUnit *SU);
40 HazardType getHazardType(SUnit *SU, int Stalls) override;
41 bool ShouldPreferAnother(SUnit* SU) override;
42 unsigned PreEmitNoops(SUnit *SU) override;
43 void EmitInstruction(SUnit *SU) override;
79 HazardType getHazardType(SUnit *SU, int Stalls) override;
80 void EmitInstruction(SUnit *SU) override;
/external/llvm/include/llvm/CodeGen/
DMachineScheduler.h205 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
209 virtual void releaseTopNode(SUnit *SU) = 0;
212 virtual void releaseBottomNode(SUnit *SU) = 0;
334 void updateQueues(SUnit *SU, bool IsTopNode);
348 void releaseSucc(SUnit *SU, SDep *SuccEdge);
349 void releaseSuccessors(SUnit *SU);
350 void releasePred(SUnit *SU, SDep *PredEdge);
351 void releasePredecessors(SUnit *SU);
421 PressureDiff &getPressureDiff(const SUnit *SU) { in getPressureDiff() argument
422 return SUPressureDiffs[SU->NodeNum]; in getPressureDiff()
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DScheduleDAGInstrs.h36 SUnit *SU; member
38 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) in VReg2SUnit()
39 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit()
51 unsigned OperandIndex, SUnit *SU) in VReg2SUnitOperIdx()
52 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
58 SUnit *SU; member
62 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} in PhysRegSUOper()
179 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass() argument
180 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) in getSchedClass()
181 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
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DResourcePriorityQueue.h84 void addNode(const SUnit *SU) override { in addNode() argument
88 void updateNode(const SUnit *SU) override {} in updateNode() argument
106 signed SUSchedulingCost (SUnit *SU);
110 void initNumRegDefsLeft(SUnit *SU);
111 void updateNumRegDefsLeft(SUnit *SU);
112 signed regPressureDelta(SUnit *SU, bool RawPressure = false);
113 signed rawRegPressureDelta (SUnit *SU, unsigned RCId);
121 void remove(SUnit *SU) override;
125 bool isResourceAvailable(SUnit *SU);
126 void reserveResources(SUnit *SU);
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DScheduleDFS.h146 unsigned getNumInstrs(const SUnit *SU) const { in getNumInstrs() argument
147 return DFSNodeData[SU->NodeNum].InstrCount; in getNumInstrs()
159 ILPValue getILP(const SUnit *SU) const { in getILP() argument
160 return ILPValue(DFSNodeData[SU->NodeNum].InstrCount, 1 + SU->getDepth()); in getILP()
170 unsigned getSubtreeID(const SUnit *SU) const { in getSubtreeID() argument
173 assert(SU->NodeNum < DFSNodeData.size() && "New Node"); in getSubtreeID()
174 return DFSNodeData[SU->NodeNum].SubtreeID; in getSubtreeID()
DLatencyPriorityQueue.h57 void addNode(const SUnit *SU) override { in addNode() argument
61 void updateNode(const SUnit *SU) override { in updateNode() argument
84 void remove(SUnit *SU) override;
93 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
94 SUnit *getSingleUnscheduledPred(SUnit *SU);
/external/eigen/blas/fortran/
Dsrotmg.f55 + SQ2,STEMP,SU,TWO,ZERO local
86 SU = ONE - SH12*SH21
88 IF (.NOT.SU.LE.ZERO) GO TO 30
93 SD1 = SD1/SU
94 SD2 = SD2/SU
95 SX1 = SX1*SU
106 SU = ONE + SH11*SH22
107 STEMP = SD2/SU
108 SD2 = SD1/SU
110 SX1 = SY1*SU
/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { in getHazardType() argument
38 MachineInstr *MI = SU->getInstr(); in getHazardType()
74 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); in getHazardType()
83 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { in EmitInstruction() argument
84 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
90 ScoreboardHazardRecognizer::EmitInstruction(SU); in EmitInstruction()

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