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Searched refs:SrcVT (Results 1 – 25 of 34) sorted by relevance

12

/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp163 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
806 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp() local
808 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits()) in PPCEmitCmp()
821 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
822 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
832 switch (SrcVT.SimpleTy) { in PPCEmitCmp()
872 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
878 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
897 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in SelectFPExt() local
900 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
[all …]
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp126 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
133 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
135 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
939 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPExt() local
942 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1013 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPTrunc() local
1016 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
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DMipsMSAInstrInfo.td3558 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3560 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3561 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3615 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3618 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3619 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3623 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3626 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3627 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3631 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
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/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp154 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
189 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
220 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
224 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
228 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1112 MVT SrcVT = RetVT; in emitAddSub() local
1139 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1237 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2728 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); in selectFPToInt() local
2729 if (SrcVT == MVT::f128) in selectFPToInt()
[all …]
DAArch64ISelDAGToDAG.cpp368 EVT SrcVT; in getExtendTypeForNode() local
370 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); in getExtendTypeForNode()
372 SrcVT = N.getOperand(0).getValueType(); in getExtendTypeForNode()
374 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
376 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
378 else if (SrcVT == MVT::i32) in getExtendTypeForNode()
380 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); in getExtendTypeForNode()
385 EVT SrcVT = N.getOperand(0).getValueType(); in getExtendTypeForNode() local
386 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
388 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
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DAArch64ISelLowering.cpp3715 EVT SrcVT = In2.getValueType(); in LowerFCOPYSIGN() local
3717 if (SrcVT.bitsLT(VT)) in LowerFCOPYSIGN()
3719 else if (SrcVT.bitsGT(VT)) in LowerFCOPYSIGN()
4908 EVT SrcVT = Src.ShuffleVec.getValueType(); in ReconstructShuffle() local
4910 if (SrcVT.getSizeInBits() == VT.getSizeInBits()) in ReconstructShuffle()
4915 EVT EltVT = SrcVT.getVectorElementType(); in ReconstructShuffle()
4919 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) { in ReconstructShuffle()
4920 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits()); in ReconstructShuffle()
4929 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits()); in ReconstructShuffle()
6584 EVT SrcVT = LHS.getValueType(); in EmitVectorComparison() local
[all …]
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp49 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) { in getZeroExtensionTypes() argument
58 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
63 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
70 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
75 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
82 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
87 SrcVT = MVT::v16i8; in getZeroExtensionTypes()
95 SrcVT = MVT::v8i16; in getZeroExtensionTypes()
100 SrcVT = MVT::v8i16; in getZeroExtensionTypes()
107 SrcVT = MVT::v8i16; in getZeroExtensionTypes()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp499 EVT SrcVT = LD->getMemoryVT(); in ExpandLoad() local
504 unsigned NumElem = SrcVT.getVectorNumElements(); in ExpandLoad()
506 EVT SrcEltVT = SrcVT.getScalarType(); in ExpandLoad()
509 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) { in ExpandLoad()
525 unsigned RemainingBytes = SrcVT.getStoreSize(); in ExpandLoad()
617 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8; in ExpandLoad()
623 SrcVT.getScalarType(), in ExpandLoad()
812 EVT SrcVT = Src.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
813 int NumSrcElements = SrcVT.getVectorNumElements(); in ExpandANY_EXTEND_VECTOR_INREG()
827 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask)); in ExpandANY_EXTEND_VECTOR_INREG()
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DFastISel.cpp1244 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectCast() local
1247 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1257 if (!TLI.isTypeLegal(SrcVT)) in selectCast()
1267 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1294 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast() local
1303 if (SrcVT == DstVT) { in selectBitCast()
1304 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1316 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); in selectBitCast()
1630 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectOperator() local
1632 if (DstVT.bitsGT(SrcVT)) in selectOperator()
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DLegalizeDAG.cpp956 EVT SrcVT = LD->getMemoryVT(); in LegalizeLoadOps() local
957 unsigned SrcWidth = SrcVT.getSizeInBits(); in LegalizeLoadOps()
964 if (SrcWidth != SrcVT.getStoreSizeInBits() && in LegalizeLoadOps()
972 (SrcVT != MVT::i1 || in LegalizeLoadOps()
977 unsigned NewWidth = SrcVT.getStoreSizeInBits(); in LegalizeLoadOps()
999 Result, DAG.getValueType(SrcVT)); in LegalizeLoadOps()
1004 DAG.getValueType(SrcVT)); in LegalizeLoadOps()
1010 assert(!SrcVT.isVector() && "Unsupported extload!"); in LegalizeLoadOps()
1092 SrcVT.getSimpleVT())) { in LegalizeLoadOps()
1121 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
[all …]
DLegalizeFloatTypes.cpp1392 EVT SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP() local
1399 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1408 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1412 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1427 SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP()
1435 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandFloatRes_XINT_TO_FP()
1454 Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT), in ExpandFloatRes_XINT_TO_FP()
DLegalizeIntegerTypes.cpp3041 EVT SrcVT = Op.getValueType(); in ExpandIntOp_UINT_TO_FP() local
3049 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 && in ExpandIntOp_UINT_TO_FP()
3050 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ in ExpandIntOp_UINT_TO_FP()
3064 if (SrcVT == MVT::i32) in ExpandIntOp_UINT_TO_FP()
3066 else if (SrcVT == MVT::i64) in ExpandIntOp_UINT_TO_FP()
3068 else if (SrcVT == MVT::i128) in ExpandIntOp_UINT_TO_FP()
3109 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); in ExpandIntOp_UINT_TO_FP()
DDAGCombiner.cpp5867 EVT SrcVT = N0.getValueType(); in CombineExtLoad() local
5908 EVT SplitSrcVT = SrcVT; in CombineExtLoad()
6284 EVT SrcVT = N0.getOperand(0).getValueType(); in visitZERO_EXTEND() local
6289 if (SrcVT.bitsLT(VT)) { in visitZERO_EXTEND()
6290 if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) && in visitZERO_EXTEND()
6301 if (SrcVT.bitsLT(VT)) { in visitZERO_EXTEND()
6304 } else if (SrcVT.bitsGT(VT)) { in visitZERO_EXTEND()
7083 EVT SrcVT = N0.getValueType(); in visitTRUNCATE() local
7084 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) && in visitTRUNCATE()
7085 TLI.isTruncateFree(SrcVT, VT)) { in visitTRUNCATE()
[all …]
DLegalizeVectorTypes.cpp1214 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_ExtendOp() local
1232 unsigned NumElements = SrcVT.getVectorNumElements(); in SplitVecRes_ExtendOp()
1234 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) { in SplitVecRes_ExtendOp()
1238 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2), in SplitVecRes_ExtendOp()
1241 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2); in SplitVecRes_ExtendOp()
1244 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) && in SplitVecRes_ExtendOp()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp181 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1363 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() local
1377 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || in ARMEmitCmp()
1378 SrcVT == MVT::i1) { in ARMEmitCmp()
1392 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) in ARMEmitCmp()
1400 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1442 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1445 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1556 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() local
1557 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectIToFP()
[all …]
/external/llvm/lib/Target/X86/
DX86FastISel.cpp96 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
570 unsigned Src, EVT SrcVT, in X86FastEmitExtend() argument
572 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend()
1064 EVT SrcVT = TLI.getValueType(DL, RV->getType()); in X86SelectRet() local
1067 if (SrcVT != DstVT) { in X86SelectRet()
1068 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) in X86SelectRet()
1076 if (SrcVT == MVT::i1) { in X86SelectRet()
1080 SrcVT = MVT::i8; in X86SelectRet()
1084 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet()
1342 MVT SrcVT = TLI.getSimpleValueType(DL, I->getOperand(0)->getType()); in X86SelectZExt() local
[all …]
DX86SelectionDAGInfo.cpp268 EVT SrcVT = Src.getValueType(); in EmitTargetCodeForMemcpy() local
274 DAG.getNode(ISD::ADD, dl, SrcVT, Src, in EmitTargetCodeForMemcpy()
276 SrcVT)), in EmitTargetCodeForMemcpy()
DX86ISelLowering.cpp5069 EVT SrcVT = V.getValueType(); in getShuffleScalarElt() local
5072 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) in getShuffleScalarElt()
12514 MVT SrcVT = Src.getSimpleValueType(); in LowerSINT_TO_FP() local
12518 if (SrcVT.isVector()) { in LowerSINT_TO_FP()
12519 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) { in LowerSINT_TO_FP()
12522 DAG.getUNDEF(SrcVT))); in LowerSINT_TO_FP()
12524 if (SrcVT.getVectorElementType() == MVT::i1) { in LowerSINT_TO_FP()
12525 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements()); in LowerSINT_TO_FP()
12532 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 && in LowerSINT_TO_FP()
12537 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) in LowerSINT_TO_FP()
[all …]
DX86ISelLowering.h925 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
DX86ISelDAGToDAG.cpp595 MVT SrcVT = N->getOperand(0).getSimpleValueType(); in PreprocessISelDAG() local
599 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
606 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT); in PreprocessISelDAG()
627 MemVT = SrcIsSSE ? SrcVT : DstVT; in PreprocessISelDAG()
/external/llvm/lib/Transforms/Scalar/
DScalarizer.cpp489 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy()); in visitBitCastInst() local
490 if (!DstVT || !SrcVT) in visitBitCastInst()
494 unsigned SrcNumElems = SrcVT->getNumElements(); in visitBitCastInst()
526 Type *MidTy = VectorType::get(SrcVT->getElementType(), FanIn); in visitBitCastInst()
/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.h102 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT,
DX86ShuffleDecode.cpp431 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT, SmallVectorImpl<int> &Mask) { in DecodeZeroExtendMask() argument
433 unsigned SrcScalarBits = SrcVT.getScalarSizeInBits(); in DecodeZeroExtendMask()
438 assert(SrcVT.getVectorNumElements() >= NumDstElts && in DecodeZeroExtendMask()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1632 EVT SrcVT = Src.getValueType(); in performUCharToFloatCombine() local
1638 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) { in performUCharToFloatCombine()
1651 !SrcVT.isVector() || in performUCharToFloatCombine()
1652 SrcVT.getVectorElementType() != MVT::i8) { in performUCharToFloatCombine()
1660 unsigned NElts = SrcVT.getVectorNumElements(); in performUCharToFloatCombine()
1661 if (!SrcVT.isSimple() && NElts != 3) in performUCharToFloatCombine()
1667 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT); in performUCharToFloatCombine()
1668 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT); in performUCharToFloatCombine()
/external/llvm/lib/CodeGen/
DCodeGenPrepare.cpp775 EVT SrcVT = TLI.getValueType(DL, CI->getOperand(0)->getType()); in OptimizeNoopCopyExpression() local
779 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
784 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
789 if (TLI.getTypeAction(CI->getContext(), SrcVT) == in OptimizeNoopCopyExpression()
791 SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT); in OptimizeNoopCopyExpression()
797 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()

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