| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 40 UXTB, enumerator
60 case AArch64_AM::UXTB: return "uxtb"; in getShiftExtendName()
127 case 0: return AArch64_AM::UXTB; in getExtendType()
154 case AArch64_AM::UXTB: return 0; break; in getExtendEncoding()
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| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 154 COMPARE(Mov(w10, Operand(w11, UXTB)), "uxtb w10, w11"); in TEST_()
155 COMPARE(Mov(x12, Operand(x13, UXTB, 1)), "ubfiz x12, x13, #1, #8"); in TEST_()
389 COMPARE(add(w0, w1, Operand(w2, UXTB)), "add w0, w1, w2, uxtb"); in TEST_()
390 COMPARE(adds(x3, x4, Operand(w5, UXTB, 1)), "adds x3, x4, w5, uxtb #1"); in TEST_()
399 COMPARE(cmn(w0, Operand(w1, UXTB, 2)), "cmn w0, w1, uxtb #2"); in TEST_()
402 COMPARE(add(w0, wcsp, Operand(w1, UXTB)), "add w0, wcsp, w1, uxtb"); in TEST_()
415 COMPARE(sub(w0, w1, Operand(w2, UXTB)), "sub w0, w1, w2, uxtb"); in TEST_()
416 COMPARE(subs(x3, x4, Operand(w5, UXTB, 1)), "subs x3, x4, w5, uxtb #1"); in TEST_()
428 COMPARE(sub(w0, wcsp, Operand(w1, UXTB)), "sub w0, wcsp, w1, uxtb"); in TEST_()
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| D | test-assembler-arm64.cc | 307 __ Mvn(w10, Operand(w2, UXTB)); in TEST()
380 __ Mov(w23, Operand(w13, UXTB)); in TEST()
564 __ Orr(w6, w0, Operand(w1, UXTB)); in TEST()
661 __ Orn(w6, w0, Operand(w1, UXTB)); in TEST()
730 __ And(w6, w0, Operand(w1, UXTB)); in TEST()
871 __ Bic(w6, w0, Operand(w1, UXTB)); in TEST()
999 __ Eor(w6, w0, Operand(w1, UXTB)); in TEST()
1068 __ Eon(w6, w0, Operand(w1, UXTB)); in TEST()
3595 __ Add(x10, x0, Operand(x1, UXTB, 0)); in TEST()
3596 __ Add(x11, x0, Operand(x1, UXTB, 1)); in TEST()
[all …]
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 521 # UXTB/UXTH
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| D | thumb2.txt | 2632 # UXTB
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| D | basic-arm-instructions.txt | 2474 # UXTB
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 656 @ UXTB/UXTH
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 97 return Operand(InputRegister32(index), UXTB); in InputOperand2_32()
125 return Operand(InputRegister64(index), UXTB); in InputOperand2_64()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 505 UXTB, enumerator
|
| /external/vixl/test/ |
| D | test-disasm-a64.cc | 159 COMPARE(Mov(w10, Operand(w11, UXTB)), "uxtb w10, w11"); in TEST()
160 COMPARE(Mov(x12, Operand(x13, UXTB, 1)), "ubfiz x12, x13, #1, #8"); in TEST()
388 COMPARE(add(w0, w1, Operand(w2, UXTB)), "add w0, w1, w2, uxtb"); in TEST()
389 COMPARE(adds(x3, x4, Operand(w5, UXTB, 1)), "adds x3, x4, w5, uxtb #1"); in TEST()
398 COMPARE(cmn(w0, Operand(w1, UXTB, 2)), "cmn w0, w1, uxtb #2"); in TEST()
401 COMPARE(add(w0, wsp, Operand(w1, UXTB)), "add w0, wsp, w1, uxtb"); in TEST()
414 COMPARE(sub(w0, w1, Operand(w2, UXTB)), "sub w0, w1, w2, uxtb"); in TEST()
415 COMPARE(subs(x3, x4, Operand(w5, UXTB, 1)), "subs x3, x4, w5, uxtb #1"); in TEST()
427 COMPARE(sub(w0, wsp, Operand(w1, UXTB)), "sub w0, wsp, w1, uxtb"); in TEST()
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| D | test-assembler-a64.cc | 300 __ Mvn(w10, Operand(w2, UXTB)); in TEST()
473 __ Mov(w23, Operand(w13, UXTB)); in TEST()
558 __ Orr(w6, w0, Operand(w1, UXTB)); in TEST()
652 __ Orn(w6, w0, Operand(w1, UXTB)); in TEST()
719 __ And(w6, w0, Operand(w1, UXTB)); in TEST()
857 __ Bic(w6, w0, Operand(w1, UXTB)); in TEST()
981 __ Eor(w6, w0, Operand(w1, UXTB)); in TEST()
1048 __ Eon(w6, w0, Operand(w1, UXTB)); in TEST()
7457 __ Add(x10, x0, Operand(x1, UXTB, 0)); in TEST()
7458 __ Add(x11, x0, Operand(x1, UXTB, 1)); in TEST()
[all …]
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 339 UXTB = 0, enumerator
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| D | assembler-arm64.cc | 2421 case UXTB: in EmitExtendShift()
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| D | simulator-arm64.cc | 946 case UXTB: in ExtendValue()
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| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_T2_32.c | 165 #define UXTB 0xb2c0 macro
695 return push_inst16(compiler, UXTB | RD3(dst) | RN3(arg2)); in emit_op_imm()
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| D | sljitNativeARM_32.c | 123 #define UXTB 0xe6ef0070 macro
1014 return push_inst(compiler, (op == SLJIT_MOV_UB ? UXTB : SXTB) | RD(dst) | RM(src2)); in emit_single_op()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 161 // EXAMPLE: ADDXre Xn, Xm, UXTB #1
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| D | AArch64ISelDAGToDAG.cpp | 387 return AArch64_AM::UXTB; in getExtendTypeForNode()
405 return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend; in getExtendTypeForNode()
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 276 UXTB = 0, enumerator
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| D | simulator-a64.cc | 355 case UXTB: in ExtendValue()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 157 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| D | ARMFastISel.cpp | 2893 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
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| D | ARMInstrInfo.td | 3377 def UXTB : AI_ext_rrot<0b01101110,
5481 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5606 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1002 return (ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB || in isExtend()
2412 .Case("uxtb", AArch64_AM::UXTB) in tryParseOptionalShiftExtend()
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| /external/vixl/doc/ |
| D | supported-instructions.md | 1395 ### UXTB ### subsection
|