| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 392 COMPARE(adds(x9, x10, Operand(x11, UXTW, 3)), "adds x9, x10, w11, uxtw #3"); in TEST_()
404 COMPARE(add(wcsp, wcsp, Operand(w4, UXTW, 2)), "add wcsp, wcsp, w4, lsl #2"); in TEST_()
418 COMPARE(subs(x9, x10, Operand(x11, UXTW, 3)), "subs x9, x10, w11, uxtw #3"); in TEST_()
430 COMPARE(sub(wcsp, wcsp, Operand(w4, UXTW, 2)), "sub wcsp, wcsp, w4, lsl #2"); in TEST_()
908 COMPARE(ldr(w0, MemOperand(x1, w2, UXTW)), "ldr w0, [x1, w2, uxtw]"); in TEST_()
909 COMPARE(ldr(w3, MemOperand(x4, w5, UXTW, 2)), "ldr w3, [x4, w5, uxtw #2]"); in TEST_()
918 COMPARE(ldr(x0, MemOperand(x1, w2, UXTW)), "ldr x0, [x1, w2, uxtw]"); in TEST_()
919 COMPARE(ldr(x3, MemOperand(x4, w5, UXTW, 3)), "ldr x3, [x4, w5, uxtw #3]"); in TEST_()
929 COMPARE(str(w0, MemOperand(x1, w2, UXTW)), "str w0, [x1, w2, uxtw]"); in TEST_()
930 COMPARE(str(w3, MemOperand(x4, w5, UXTW, 2)), "str w3, [x4, w5, uxtw #2]"); in TEST_()
[all …]
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| D | test-assembler-arm64.cc | 311 __ Mvn(x14, Operand(w2, UXTW, 4)); in TEST()
384 __ Mov(x27, Operand(w13, UXTW, 4)); in TEST()
566 __ Orr(w8, w0, Operand(w1, UXTW, 2)); in TEST()
663 __ Orn(w8, w0, Operand(w1, UXTW, 2)); in TEST()
732 __ And(w8, w0, Operand(w1, UXTW, 2)); in TEST()
873 __ Bic(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1001 __ Eor(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1070 __ Eon(w8, w0, Operand(w1, UXTW, 2)); in TEST()
3598 __ Add(x13, x0, Operand(x1, UXTW, 4)); in TEST()
3794 __ Neg(w13, Operand(w0, UXTW, 4)); in TEST()
[all …]
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 42 UXTW, enumerator
62 case AArch64_AM::UXTW: return "uxtw"; in getShiftExtendName()
129 case 2: return AArch64_AM::UXTW; in getExtendType()
156 case AArch64_AM::UXTW: return 2; break; in getExtendEncoding()
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| /external/vixl/test/ |
| D | test-disasm-a64.cc | 391 COMPARE(adds(x9, x10, Operand(x11, UXTW, 3)), "adds x9, x10, w11, uxtw #3"); in TEST()
403 COMPARE(add(wsp, wsp, Operand(w4, UXTW, 2)), "add wsp, wsp, w4, lsl #2"); in TEST()
417 COMPARE(subs(x9, x10, Operand(x11, UXTW, 3)), "subs x9, x10, w11, uxtw #3"); in TEST()
429 COMPARE(sub(wsp, wsp, Operand(w4, UXTW, 2)), "sub wsp, wsp, w4, lsl #2"); in TEST()
1023 COMPARE(ldr(w0, MemOperand(x1, w2, UXTW)), "ldr w0, [x1, w2, uxtw]"); in TEST()
1024 COMPARE(ldr(w3, MemOperand(x4, w5, UXTW, 2)), "ldr w3, [x4, w5, uxtw #2]"); in TEST()
1033 COMPARE(ldr(x0, MemOperand(x1, w2, UXTW)), "ldr x0, [x1, w2, uxtw]"); in TEST()
1034 COMPARE(ldr(x3, MemOperand(x4, w5, UXTW, 3)), "ldr x3, [x4, w5, uxtw #3]"); in TEST()
1044 COMPARE(str(w0, MemOperand(x1, w2, UXTW)), "str w0, [x1, w2, uxtw]"); in TEST()
1045 COMPARE(str(w3, MemOperand(x4, w5, UXTW, 2)), "str w3, [x4, w5, uxtw #2]"); in TEST()
[all …]
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| D | test-simulator-a64.cc | 228 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); in Test1Op_Helper()
335 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in Test2Op_Helper()
339 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in Test2Op_Helper()
457 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in Test3Op_Helper()
461 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in Test3Op_Helper()
465 __ Ldr(fa, MemOperand(inputs_base, index_a, UXTW, index_shift)); in Test3Op_Helper()
590 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in TestCmp_Helper()
594 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); in TestCmp_Helper()
717 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); in TestCmpZero_Helper()
834 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); in TestFPToFixed_Helper()
[all …]
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| D | test-assembler-a64.cc | 304 __ Mvn(x14, Operand(w2, UXTW, 4)); in TEST()
477 __ Mov(x27, Operand(w13, UXTW, 4)); in TEST()
560 __ Orr(w8, w0, Operand(w1, UXTW, 2)); in TEST()
654 __ Orn(w8, w0, Operand(w1, UXTW, 2)); in TEST()
721 __ And(w8, w0, Operand(w1, UXTW, 2)); in TEST()
859 __ Bic(w8, w0, Operand(w1, UXTW, 2)); in TEST()
983 __ Eor(w8, w0, Operand(w1, UXTW, 2)); in TEST()
1050 __ Eon(w8, w0, Operand(w1, UXTW, 2)); in TEST()
2845 __ Ldr(h3, MemOperand(x17, x18, UXTW, 1)); in TEST()
2850 __ Ldr(s17, MemOperand(x17, x18, UXTW, 2)); in TEST()
[all …]
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 375 __ Ldr(result, MemOperand(buffer, offset, UXTW)); \
389 __ asm_instr(result, MemOperand(buffer, offset, UXTW)); \
403 __ asm_instr(result, MemOperand(buffer, offset, UXTW)); \
417 __ Str(value, MemOperand(buffer, offset, UXTW)); \
431 __ asm_instr(value, MemOperand(buffer, offset, UXTW)); \
445 __ asm_instr(value, MemOperand(buffer, offset, UXTW)); \
1323 __ Add(temp, temp, Operand(input, UXTW, 2)); in AssembleArchTableSwitch()
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| /external/v8/src/regexp/arm64/ |
| D | regexp-macro-assembler-arm64.cc | 192 __ Add(x10, code_pointer(), Operand(w10, UXTW)); in Backtrack()
575 __ Ldrb(w11, MemOperand(x11, w10, UXTW)); in CheckBitInTable()
656 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); in CheckSpecialCharacterClass()
669 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); in CheckSpecialCharacterClass()
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| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 398 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
481 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
534 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
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| D | disasm-arm64.cc | 1616 (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) || in SubstituteExtendField()
1640 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| D | constants-arm64.h | 341 UXTW = 2, enumerator
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| D | simulator-arm64.cc | 952 case UXTW: in ExtendValue()
1579 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | assembler-arm64.cc | 2423 case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
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| D | code-stubs-arm64.cc | 2455 __ Add(x2, start, Operand(w10, UXTW)); in Generate()
2460 __ Add(x3, x2, Operand(w10, UXTW)); in Generate()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 675 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
699 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
759 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
796 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
818 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
999 Addr.getExtendType() == AArch64_AM::UXTW ) in simplifyAddress()
1010 if (Addr.getExtendType() == AArch64_AM::UXTW) in simplifyAddress()
1778 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitLoad()
2030 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitStore()
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| D | AArch64ISelDAGToDAG.cpp | 391 return AArch64_AM::UXTW; in getExtendTypeForNode()
409 return AArch64_AM::UXTW; in getExtendTypeForNode()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1048 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1054 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 507 UXTW, enumerator
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1004 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
1039 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
1575 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
2414 .Case("uxtw", AArch64_AM::UXTW) in tryParseOptionalShiftExtend()
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| /external/vixl/src/vixl/a64/ |
| D | disasm-a64.cc | 3347 (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) || in SubstituteExtendField()
3371 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| D | assembler-a64.cc | 372 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); in ToExtendedRegister()
391 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
442 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
4861 case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
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| D | constants-a64.h | 278 UXTW = 2, enumerator
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| D | simulator-a64.cc | 361 case UXTW: in ExtendValue()
1067 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| /external/v8/src/crankshaft/arm64/ |
| D | lithium-codegen-arm64.cc | 1384 __ Ldr(result, MemOperand(arguments, result, UXTW, kPointerSizeLog2)); in DoAccessArgumentsAt()
1386 __ Ldr(result, MemOperand(arguments, length, UXTW, kPointerSizeLog2)); in DoAccessArgumentsAt()
1393 __ Ldr(result, MemOperand(arguments, result, UXTW, kPointerSizeLog2)); in DoAccessArgumentsAt()
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| /external/vixl/doc/ |
| D | supported-instructions.md | 1409 ### UXTW ### subsection
|