| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 30 if (SUnits[su].getInstr()->isCall()) in postprocessDAG()
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) in postprocessDAG()
44 if (!SU || !SU->getInstr()) in isResourceAvailable()
49 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
51 if (!ResourcesModel->canReserveResources(SU->getInstr())) in isResourceAvailable()
101 switch (SU->getInstr()->getOpcode()) { in reserveResources()
103 ResourcesModel->reserveResources(SU->getInstr()); in reserveResources()
124 DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
249 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
281 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
[all …]
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| D | HexagonVLIWPacketizer.cpp | 379 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
547 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
633 MachineInstr* TempMI = TempSU->getInstr(); in canPromoteToNewValueStore()
646 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) in canPromoteToNewValueStore()
698 MachineInstr *PacketMI = PacketSU->getInstr(); in canPromoteToNewValue()
729 const MachineInstr *PI = PacketSU->getInstr(); in canPromoteToDotNew()
1130 MachineInstr *I = SUI->getInstr(); in isLegalToPacketizeTogether()
1131 MachineInstr *J = SUJ->getInstr(); in isLegalToPacketizeTogether()
1173 MachineInstr *PI = PacketSU->getInstr(); in isLegalToPacketizeTogether()
1420 MachineInstr *I = SUI->getInstr(); in isLegalToPruneDependencies()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600MachineScheduler.cpp | 163 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
164 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
198 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
223 MachineInstr *MI = SU->getInstr(); in getAluKind()
297 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
326 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
328 && (!AnyALU || !TII->isVectorOnly(SU->getInstr())) in PopInst()
398 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
447 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
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| D | R600Packetizer.cpp | 189 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr(); in isLegalToPacketizeTogether()
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| D | SILoadStoreOptimizer.cpp | 299 return Read2.getInstr(); in mergeRead2Pair()
376 return Write2.getInstr(); in mergeWrite2Pair()
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 248 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
275 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
278 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
291 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
311 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
317 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
386 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
424 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
470 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
495 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
[all …]
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| D | MachineScheduler.cpp | 700 MachineInstr *MI = SU->getInstr(); in schedule()
1003 = LI.Query(LIS->getInstructionIndex(SU->getInstr())); in updatePressureDiffs()
1009 << *SU->getInstr(); in updatePressureDiffs()
1197 LI.Query(LIS->getInstructionIndex(SU->getInstr())); in computeCyclicCriticalPath()
1229 MachineInstr *MI = SU->getInstr(); in scheduleMI()
1322 if (TII->getMemOpBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI)) in clusterNeighboringLoads()
1337 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength) in clusterNeighboringLoads()
1368 if (!SU->getInstr()->mayLoad()) in apply()
1429 MachineInstr *Branch = ExitSU.getInstr(); in apply()
1438 MachineInstr *Pred = SU.getInstr(); in apply()
[all …]
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| D | SlotIndexes.cpp | 184 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
222 if (itr->getInstr()) { in dump()
223 dbgs() << *itr->getInstr(); in dump()
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| D | CriticalAntiDepBreaker.cpp | 441 MISUnitMap[SU->getInstr()] = SU; in BreakAntiDependencies()
462 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
573 CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
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| D | DFAPacketizer.cpp | 218 MIToSUnit[SU->getInstr()] = SU; in PacketizeMIs()
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| D | AggressiveAntiDepBreaker.cpp | 756 MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(), in BreakAntiDependencies()
775 CriticalPathMI = CriticalPathSU->getInstr(); in BreakAntiDependencies()
820 CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr; in BreakAntiDependencies()
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| D | PostRASchedulerList.cpp | 663 BB->splice(RegionEnd, BB, SU->getInstr()); in EmitSchedule()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMHazardRecognizer.cpp | 38 MachineInstr *MI = SU->getInstr(); in getHazardType()
84 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
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| D | Thumb2ITBlockPass.cpp | 204 MachineBasicBlock::iterator InsertPos = MIB.getInstr(); in InsertITInstructions()
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| D | Thumb1FrameLowering.cpp | 549 MBB.erase(MIB.getInstr()); in emitPopSpecialFixUp()
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| D | ARMLoadStoreOptimizer.cpp | 770 return MIB.getInstr(); in CreateLoadStoreMulti()
792 return MIB.getInstr(); in CreateLoadStoreDouble()
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| /external/llvm/include/llvm/CodeGen/ |
| D | SlotIndexes.h | 46 MachineInstr* getInstr() const { return mi; } in getInstr() function
428 return index.isValid() ? index.listEntry()->getInstr() : nullptr;
437 if (I->getInstr())
623 assert(miEntry->getInstr() == mi && "Instruction indexes broken.");
638 assert(miEntry->getInstr() == mi &&
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| D | ScheduleDAGInstrs.h | 181 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
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| D | ScheduleDAG.h | 406 MachineInstr *getInstr() const {
585 if (SU->isInstr()) return &SU->getInstr()->getDesc();
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| D | MachineInstrBuilder.h | 62 MachineInstr *getInstr() const { return MI; } in getInstr() function
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 440 .getInstr(); in loadImmediate()
444 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr(); in loadImmediate()
452 .getInstr(); in loadImmediate()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 328 MachineInstr *MI = SU->getInstr(); in getHazardType()
386 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
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| /external/llvm/include/llvm/Analysis/ |
| D | LoopAccessAnalysis.h | 57 const Instruction *getInstr() const { return Instr; } in getInstr() function
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| /external/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 497 .getInstr(); in adjustCallSequence()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.cpp | 361 MovMI = MIB.getInstr(); in copyPhysReg()
|