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Searched refs:getOpcode (Results 1 – 25 of 656) sorted by relevance

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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/writer/
DInstructionWriter.java99 writer.write(getOpcodeValue(instruction.getOpcode())); in write()
108 writer.write(getOpcodeValue(instruction.getOpcode())); in write()
117 writer.write(getOpcodeValue(instruction.getOpcode())); in write()
126 writer.write(getOpcodeValue(instruction.getOpcode())); in write()
135 writer.write(getOpcodeValue(instruction.getOpcode())); in write()
144 writer.write(getOpcodeValue(instruction.getOpcode())); in write()
154 writer.write(getOpcodeValue(instruction.getOpcode())); in write()
164 writer.write(getOpcodeValue(instruction.getOpcode())); in write()
174 writer.write(getOpcodeValue(instruction.getOpcode())); in write()
184 writer.write(getOpcodeValue(instruction.getOpcode())); in write()
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/external/llvm/unittests/Transforms/Utils/
DIntegerDivision.cpp42 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv); in TEST()
47 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr); in TEST()
50 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::Sub); in TEST()
72 EXPECT_TRUE(BB->front().getOpcode() == Instruction::UDiv); in TEST()
77 EXPECT_TRUE(BB->front().getOpcode() == Instruction::ICmp); in TEST()
80 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::PHI); in TEST()
102 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem); in TEST()
107 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr); in TEST()
110 EXPECT_TRUE(Remainder && Remainder->getOpcode() == Instruction::Sub); in TEST()
132 EXPECT_TRUE(BB->front().getOpcode() == Instruction::URem); in TEST()
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/external/llvm/lib/Target/PowerPC/
DPPCBranchSelector.cpp143 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm()) in runOnMachineFunction()
145 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) && in runOnMachineFunction()
148 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ || in runOnMachineFunction()
149 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) && in runOnMachineFunction()
188 if (I->getOpcode() == PPC::BCC) { in runOnMachineFunction()
199 } else if (I->getOpcode() == PPC::BC) { in runOnMachineFunction()
202 } else if (I->getOpcode() == PPC::BCn) { in runOnMachineFunction()
205 } else if (I->getOpcode() == PPC::BDNZ) { in runOnMachineFunction()
207 } else if (I->getOpcode() == PPC::BDNZ8) { in runOnMachineFunction()
209 } else if (I->getOpcode() == PPC::BDZ) { in runOnMachineFunction()
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DPPCEarlyReturn.cpp66 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
82 if (J->getOpcode() == PPC::B) { in processBlock()
86 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode())) in processBlock()
94 } else if (J->getOpcode() == PPC::BCC) { in processBlock()
108 } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) { in processBlock()
114 TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn)) in processBlock()
/external/llvm/include/llvm/IR/
DOperator.h48 unsigned getOpcode() const { in getOpcode() function
50 return I->getOpcode(); in getOpcode()
51 return cast<ConstantExpr>(this)->getOpcode(); in getOpcode()
56 static unsigned getOpcode(const Value *V) { in getOpcode() function
58 return I->getOpcode(); in getOpcode()
60 return CE->getOpcode(); in getOpcode()
107 return I->getOpcode() == Instruction::Add || in classof()
108 I->getOpcode() == Instruction::Sub || in classof()
109 I->getOpcode() == Instruction::Mul || in classof()
110 I->getOpcode() == Instruction::Shl; in classof()
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DInstruction.h105 unsigned getOpcode() const { return getValueID() - InstructionVal; }
107 const char *getOpcodeName() const { return getOpcodeName(getOpcode()); }
108 bool isTerminator() const { return isTerminator(getOpcode()); }
109 bool isBinaryOp() const { return isBinaryOp(getOpcode()); }
110 bool isShift() { return isShift(getOpcode()); }
111 bool isCast() const { return isCast(getOpcode()); }
112 bool isFuncletPad() const { return isFuncletPad(getOpcode()); }
132 return getOpcode() == Shl || getOpcode() == LShr;
137 return getOpcode() == AShr;
328 bool isCommutative() const { return isCommutative(getOpcode()); }
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/external/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h159 inline unsigned getOpcode() const;
441 unsigned getOpcode() const { return (unsigned short)NodeType; }
932 inline unsigned SDValue::getOpcode() const {
933 return Node->getOpcode();
1051 return isBinOpWithFlags(N->getOpcode());
1099 return N->getOpcode() == ISD::ADDRSPACECAST;
1186 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1193 return N->getOpcode() == ISD::LOAD ||
1194 N->getOpcode() == ISD::STORE ||
1195 N->getOpcode() == ISD::PREFETCH ||
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/external/llvm/lib/Target/Hexagon/
DHexagonNewValueJump.cpp132 if (II->getOpcode() == TargetOpcode::KILL) in INITIALIZE_PASS_DEPENDENCY()
182 if (MII->getOpcode() == Hexagon::J2_call) in commonChecksToProhibitNewValueJump()
196 if (MII->getOpcode() == TargetOpcode::KILL || in commonChecksToProhibitNewValueJump()
197 MII->getOpcode() == TargetOpcode::PHI || in commonChecksToProhibitNewValueJump()
198 MII->getOpcode() == TargetOpcode::COPY) in commonChecksToProhibitNewValueJump()
205 if (MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
206 MII->getOpcode() == Hexagon::STriw_pred) in commonChecksToProhibitNewValueJump()
230 ((MI->getOpcode() == Hexagon::C2_cmpeqi || in canCompareBeNewValueJump()
231 MI->getOpcode() == Hexagon::C2_cmpgti) && in canCompareBeNewValueJump()
248 if (def->getOpcode() == TargetOpcode::COPY) in canCompareBeNewValueJump()
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/external/llvm/include/llvm/MC/
DMCInstrAnalysis.h35 return Info->get(Inst.getOpcode()).isBranch(); in isBranch()
39 return Info->get(Inst.getOpcode()).isConditionalBranch(); in isConditionalBranch()
43 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); in isUnconditionalBranch()
47 return Info->get(Inst.getOpcode()).isIndirectBranch(); in isIndirectBranch()
51 return Info->get(Inst.getOpcode()).isCall(); in isCall()
55 return Info->get(Inst.getOpcode()).isReturn(); in isReturn()
59 return Info->get(Inst.getOpcode()).isTerminator(); in isTerminator()
/external/dexmaker/src/dx/java/com/android/dx/ssa/
DNormalSsaInsn.java128 public Rop getOpcode() { in getOpcode() method in NormalSsaInsn
129 return insn.getOpcode(); in getOpcode()
143 if (insn.getOpcode().getOpcode() == RegOps.MARK_LOCAL) { in getLocalAssignment()
180 return insn.getOpcode().getOpcode() == RegOps.MOVE; in isNormalMoveInsn()
186 return insn.getOpcode().getOpcode() == RegOps.MOVE_EXCEPTION; in isMoveException()
218 Rop opcode = getOpcode(); in hasSideEffect()
227 switch (opcode.getOpcode()) { in hasSideEffect()
/external/llvm/lib/Target/AMDGPU/
DR600EmitClauseMarkers.cpp42 switch (MI->getOpcode()) { in OccupiedDwords()
56 if (TII->isLDSRetInstr(MI->getOpcode())) in OccupiedDwords()
60 TII->isCubeOp(MI->getOpcode()) || in OccupiedDwords()
61 TII->isReductionOp(MI->getOpcode())) in OccupiedDwords()
75 if (TII->isALUInstr(MI->getOpcode())) in isALU()
77 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) in isALU()
79 switch (MI->getOpcode()) { in isALU()
93 switch (MI->getOpcode()) { in IsTrivialInst()
122 if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4) in SubstituteKCacheBank()
127 assert((TII->isALUInstr(MI->getOpcode()) || in SubstituteKCacheBank()
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DR600Packetizer.cpp76 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
90 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); in getPreviousVector()
93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); in getPreviousVector()
102 if (BI->getOpcode() == AMDGPU::DOT4_r600 || in getPreviousVector()
103 BI->getOpcode() == AMDGPU::DOT4_eg) { in getPreviousVector()
140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); in substitutePV()
175 if (!TII->isALUInstr(MI->getOpcode())) in isSoloInstruction()
177 if (MI->getOpcode() == AMDGPU::GROUP_BARRIER) in isSoloInstruction()
181 if (TII->isLDSInstr(MI->getOpcode())) in isSoloInstruction()
193 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel), in isLegalToPacketizeTogether()
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DR600InstrInfo.cpp39 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG; in isTrig()
43 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; in isVector()
162 if (isALUInstr(MI->getOpcode())) in canBeConsideredALU()
164 if (isVector(*MI) || isCubeOp(MI->getOpcode())) in canBeConsideredALU()
166 switch (MI->getOpcode()) { in canBeConsideredALU()
186 return isTransOnly(MI->getOpcode()); in isTransOnly()
194 return isVectorOnly(MI->getOpcode()); in isVectorOnly()
209 usesVertexCache(MI->getOpcode()); in usesVertexCache()
220 usesVertexCache(MI->getOpcode())) || in usesTextureCache()
221 usesTextureCache(MI->getOpcode()); in usesTextureCache()
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/external/llvm/lib/Target/Sparc/
DDelaySlotFiller.cpp119 (MI->getOpcode() == SP::RESTORErr in runOnMachineBasicBlock()
120 || MI->getOpcode() == SP::RESTOREri)) { in runOnMachineBasicBlock()
128 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD in runOnMachineBasicBlock()
129 || MI->getOpcode() == SP::FCMPQ)) { in runOnMachineBasicBlock()
180 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL) in findDelayInstr()
183 if (slot->getOpcode() == SP::RETL) { in findDelayInstr()
187 if (J->getOpcode() == SP::RESTORErr in findDelayInstr()
188 || J->getOpcode() == SP::RESTOREri) { in findDelayInstr()
282 switch(MI->getOpcode()) { in insertCallDefsUses()
321 if (MO.isImplicit() && MI->getOpcode() == SP::RETL) in insertDefsUses()
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DSparcISelDAGToDAG.cpp85 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRri()
86 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRri()
87 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in SelectADDRri()
90 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRri()
106 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
111 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
123 if (Addr.getOpcode() == ISD::FrameIndex) return false; in SelectADDRrr()
124 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRrr()
125 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRrr()
126 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in SelectADDRrr()
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/external/llvm/lib/Transforms/InstCombine/
DInstCombineShifts.cpp108 switch (I->getOpcode()) { in CanEvaluateShifted()
206 switch (I->getOpcode()) { in GetShiftedValue()
323 bool isLeftShift = I.getOpcode() == Instruction::Shl; in FoldShiftByConstant()
338 if (I.getOpcode() != Instruction::AShr && in FoldShiftByConstant()
356 if (BO->getOpcode() == Instruction::Mul && isLeftShift) in FoldShiftByConstant()
382 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName()); in FoldShiftByConstant()
396 if (I.getOpcode() == Instruction::Shl) in FoldShiftByConstant()
399 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift"); in FoldShiftByConstant()
418 switch (Op0BO->getOpcode()) { in FoldShiftByConstant()
432 Value *X = Builder->CreateBinOp(Op0BO->getOpcode(), YS, V1, in FoldShiftByConstant()
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/external/smali/smalidea/src/test/java/org/jf/smalidea/dexlib/
DSmalideaMethodTest.java119 Assert.assertEquals(Opcode.GOTO, instruction.getOpcode()); in testSmalideaMethod()
125 Assert.assertEquals(Opcode.RETURN_VOID, instruction.getOpcode()); in testSmalideaMethod()
130 Assert.assertEquals(Opcode.CONST_4, instruction.getOpcode()); in testSmalideaMethod()
137 Assert.assertEquals(Opcode.MONITOR_ENTER, instruction.getOpcode()); in testSmalideaMethod()
143 Assert.assertEquals(Opcode.MOVE, instruction.getOpcode()); in testSmalideaMethod()
150 Assert.assertEquals(Opcode.GOTO_16, instruction.getOpcode()); in testSmalideaMethod()
156 Assert.assertEquals(Opcode.SGET, instruction.getOpcode()); in testSmalideaMethod()
164 Assert.assertEquals(Opcode.CONST_HIGH16, instruction.getOpcode()); in testSmalideaMethod()
173 Assert.assertEquals(Opcode.CONST_WIDE_HIGH16, instruction.getOpcode()); in testSmalideaMethod()
181 Assert.assertEquals(Opcode.CONST_WIDE_16, instruction.getOpcode()); in testSmalideaMethod()
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/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp136 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
573 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
581 switch (Op.getOpcode()) { in isNegatibleForFree()
635 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
644 switch (Op.getOpcode()) { in GetNegatedExpression()
687 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
693 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
700 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
718 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
725 if (N.getOpcode() != ISD::SELECT_CC || in isSetCCEquivalent()
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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/builder/
DMutableMethodImplementation.java86 final Opcode opcode = instruction.getOpcode(); in MutableMethodImplementation()
350 if (instruction.getOpcode() != Opcode.NOP) {
363 switch (instruction.getOpcode()) {
374 if (targetInstruction.getOpcode() == Opcode.NOP) {
383 targetInstruction.getOpcode() != Opcode.PACKED_SWITCH_PAYLOAD) ||
385 targetInstruction.getOpcode() != Opcode.SPARSE_SWITCH_PAYLOAD)) {
411 switch (instruction.getOpcode()) {
454 if (previousInstruction.getOpcode() == Opcode.NOP) {
555 switch (instruction.getOpcode().format) {
660 …ow new ExceptionWithContext("Instruction format %s not supported", instruction.getOpcode().format);
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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyRegStackify.cpp96 if (Def->getOpcode() == TargetOpcode::PHI) in ImposeStackOrdering()
140 if (Insert->getOpcode() == TargetOpcode::PHI) in runOnMachineFunction()
145 if (Insert->getOpcode() == TargetOpcode::INLINEASM) in runOnMachineFunction()
174 if (Def->getOpcode() == TargetOpcode::IMPLICIT_DEF) in runOnMachineFunction()
179 if (Def->getOpcode() == TargetOpcode::INLINEASM) in runOnMachineFunction()
183 if (Def->getOpcode() == TargetOpcode::PHI) in runOnMachineFunction()
188 if (Def->getOpcode() == WebAssembly::ARGUMENT_I32 || in runOnMachineFunction()
189 Def->getOpcode() == WebAssembly::ARGUMENT_I64 || in runOnMachineFunction()
190 Def->getOpcode() == WebAssembly::ARGUMENT_F32 || in runOnMachineFunction()
191 Def->getOpcode() == WebAssembly::ARGUMENT_F64) in runOnMachineFunction()
/external/llvm/lib/Target/AArch64/
DAArch64BranchRelaxation.cpp302 switch (MI->getOpcode()) { in getDestBlock()
355 assert(MI->getOpcode() == AArch64::Bcc && "Unexpected opcode!"); in invertBccCondition()
385 BMI->getOpcode() == AArch64::B) { in fixupConditionalBranch()
395 getBranchDisplacementBits(MI->getOpcode()))) { in fixupConditionalBranch()
399 unsigned OpNum = (MI->getOpcode() == AArch64::TBZW || in fixupConditionalBranch()
400 MI->getOpcode() == AArch64::TBNZW || in fixupConditionalBranch()
401 MI->getOpcode() == AArch64::TBZX || in fixupConditionalBranch()
402 MI->getOpcode() == AArch64::TBNZX) in fixupConditionalBranch()
406 MI->setDesc(TII->get(getOppositeConditionOpcode(MI->getOpcode()))); in fixupConditionalBranch()
407 if (MI->getOpcode() == AArch64::Bcc) in fixupConditionalBranch()
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/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64ExternalSymbolizer.cpp91 } else if (MI.getOpcode() == AArch64::ADRP) { in tryAddingSymbolicOperand()
104 } else if (MI.getOpcode() == AArch64::ADDXri || in tryAddingSymbolicOperand()
105 MI.getOpcode() == AArch64::LDRXui || in tryAddingSymbolicOperand()
106 MI.getOpcode() == AArch64::LDRXl || in tryAddingSymbolicOperand()
107 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
108 if (MI.getOpcode() == AArch64::ADDXri) in tryAddingSymbolicOperand()
110 else if (MI.getOpcode() == AArch64::LDRXui) in tryAddingSymbolicOperand()
112 if (MI.getOpcode() == AArch64::LDRXl) { in tryAddingSymbolicOperand()
116 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
125 MI.getOpcode() == AArch64::ADDXri ? 0x91000000: 0xF9400000; in tryAddingSymbolicOperand()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelDAGToDAG.cpp103 if (Addr.getOpcode() == ISD::FrameIndex) { in SelectADDRParam()
111 } else if (Addr.getOpcode() == ISD::ADD) { in SelectADDRParam()
122 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDR()
123 Addr.getOpcode() == ISD::TargetGlobalAddress) { in SelectADDR()
131 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDR64()
132 Addr.getOpcode() == ISD::TargetGlobalAddress) { in SelectADDR64()
136 if (Addr.getOpcode() == ISD::FrameIndex) { in SelectADDR64()
144 } else if (Addr.getOpcode() == ISD::ADD) { in SelectADDR64()
155 unsigned int Opc = N->getOpcode(); in Select()
320 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDR8BitOffset()
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/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp114 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS) in CanTailMerge()
161 if (LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
164 } else if (LastInst->getOpcode() == NVPTX::CBranch) { in AnalyzeBranch()
182 if (SecondLastInst->getOpcode() == NVPTX::CBranch && in AnalyzeBranch()
183 LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
192 if (SecondLastInst->getOpcode() == NVPTX::GOTO && in AnalyzeBranch()
193 LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
210 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch) in RemoveBranch()
221 if (I->getOpcode() != NVPTX::CBranch) in RemoveBranch()
/external/llvm/lib/Analysis/
DCostModel.cpp171 unsigned Opcode = BinOp->getOpcode(); in matchPairwiseReductionAtLevel()
218 else if (NextLevelBinOp->getOpcode() != Opcode) in matchPairwiseReductionAtLevel()
282 Opcode = RdxStart->getOpcode(); in matchPairwiseReduction()
318 unsigned RdxOpcode = RdxStart->getOpcode(); in matchVectorSplittingReduction()
345 if (BinOp->getOpcode() != RdxOpcode) in matchVectorSplittingReduction()
382 switch (I->getOpcode()) { in getInstructionCost()
389 return TTI->getCFInstrCost(I->getOpcode()); in getInstructionCost()
413 return TTI->getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, in getInstructionCost()
419 return TTI->getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy); in getInstructionCost()
424 return TTI->getCmpSelInstrCost(I->getOpcode(), ValTy); in getInstructionCost()
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