1 //===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "NVPTX.h"
15 #include "NVPTXInstrInfo.h"
16 #include "NVPTXTargetMachine.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/Function.h"
22
23 using namespace llvm;
24
25 #define GET_INSTRINFO_CTOR_DTOR
26 #include "NVPTXGenInstrInfo.inc"
27
28 // Pin the vtable to this file.
anchor()29 void NVPTXInstrInfo::anchor() {}
30
NVPTXInstrInfo()31 NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}
32
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const33 void NVPTXInstrInfo::copyPhysReg(
34 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
35 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
36 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
39
40 if (DestRC->getSize() != SrcRC->getSize())
41 report_fatal_error("Copy one register into another with a different width");
42
43 unsigned Op;
44 if (DestRC == &NVPTX::Int1RegsRegClass) {
45 Op = NVPTX::IMOV1rr;
46 } else if (DestRC == &NVPTX::Int16RegsRegClass) {
47 Op = NVPTX::IMOV16rr;
48 } else if (DestRC == &NVPTX::Int32RegsRegClass) {
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
50 : NVPTX::BITCONVERT_32_F2I);
51 } else if (DestRC == &NVPTX::Int64RegsRegClass) {
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
53 : NVPTX::BITCONVERT_64_F2I);
54 } else if (DestRC == &NVPTX::Float32RegsRegClass) {
55 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
56 : NVPTX::BITCONVERT_32_I2F);
57 } else if (DestRC == &NVPTX::Float64RegsRegClass) {
58 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
59 : NVPTX::BITCONVERT_64_I2F);
60 } else {
61 llvm_unreachable("Bad register copy");
62 }
63 BuildMI(MBB, I, DL, get(Op), DestReg)
64 .addReg(SrcReg, getKillRegState(KillSrc));
65 }
66
isMoveInstr(const MachineInstr & MI,unsigned & SrcReg,unsigned & DestReg) const67 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
68 unsigned &DestReg) const {
69 // Look for the appropriate part of TSFlags
70 bool isMove = false;
71
72 unsigned TSFlags =
73 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
74 isMove = (TSFlags == 1);
75
76 if (isMove) {
77 MachineOperand dest = MI.getOperand(0);
78 MachineOperand src = MI.getOperand(1);
79 assert(dest.isReg() && "dest of a movrr is not a reg");
80 assert(src.isReg() && "src of a movrr is not a reg");
81
82 SrcReg = src.getReg();
83 DestReg = dest.getReg();
84 return true;
85 }
86
87 return false;
88 }
89
isLoadInstr(const MachineInstr & MI,unsigned & AddrSpace) const90 bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
91 unsigned &AddrSpace) const {
92 bool isLoad = false;
93 unsigned TSFlags =
94 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
95 isLoad = (TSFlags == 1);
96 if (isLoad)
97 AddrSpace = getLdStCodeAddrSpace(MI);
98 return isLoad;
99 }
100
isStoreInstr(const MachineInstr & MI,unsigned & AddrSpace) const101 bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
102 unsigned &AddrSpace) const {
103 bool isStore = false;
104 unsigned TSFlags =
105 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
106 isStore = (TSFlags == 1);
107 if (isStore)
108 AddrSpace = getLdStCodeAddrSpace(MI);
109 return isStore;
110 }
111
CanTailMerge(const MachineInstr * MI) const112 bool NVPTXInstrInfo::CanTailMerge(const MachineInstr *MI) const {
113 unsigned addrspace = 0;
114 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
115 return false;
116 if (isLoadInstr(*MI, addrspace))
117 if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
118 return false;
119 if (isStoreInstr(*MI, addrspace))
120 if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
121 return false;
122 return true;
123 }
124
125 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
126 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
127 /// implemented for a target). Upon success, this returns false and returns
128 /// with the following information in various cases:
129 ///
130 /// 1. If this block ends with no branches (it just falls through to its succ)
131 /// just return false, leaving TBB/FBB null.
132 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
133 /// the destination block.
134 /// 3. If this block ends with an conditional branch and it falls through to
135 /// an successor block, it sets TBB to be the branch destination block and a
136 /// list of operands that evaluate the condition. These
137 /// operands can be passed to other TargetInstrInfo methods to create new
138 /// branches.
139 /// 4. If this block ends with an conditional branch and an unconditional
140 /// block, it returns the 'true' destination in TBB, the 'false' destination
141 /// in FBB, and a list of operands that evaluate the condition. These
142 /// operands can be passed to other TargetInstrInfo methods to create new
143 /// branches.
144 ///
145 /// Note that RemoveBranch and InsertBranch must be implemented to support
146 /// cases where this method returns success.
147 ///
AnalyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const148 bool NVPTXInstrInfo::AnalyzeBranch(
149 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
150 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
151 // If the block has no terminators, it just falls into the block after it.
152 MachineBasicBlock::iterator I = MBB.end();
153 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
154 return false;
155
156 // Get the last instruction in the block.
157 MachineInstr *LastInst = I;
158
159 // If there is only one terminator instruction, process it.
160 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
161 if (LastInst->getOpcode() == NVPTX::GOTO) {
162 TBB = LastInst->getOperand(0).getMBB();
163 return false;
164 } else if (LastInst->getOpcode() == NVPTX::CBranch) {
165 // Block ends with fall-through condbranch.
166 TBB = LastInst->getOperand(1).getMBB();
167 Cond.push_back(LastInst->getOperand(0));
168 return false;
169 }
170 // Otherwise, don't know what this is.
171 return true;
172 }
173
174 // Get the instruction before it if it's a terminator.
175 MachineInstr *SecondLastInst = I;
176
177 // If there are three terminators, we don't know what sort of block this is.
178 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
179 return true;
180
181 // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
182 if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
183 LastInst->getOpcode() == NVPTX::GOTO) {
184 TBB = SecondLastInst->getOperand(1).getMBB();
185 Cond.push_back(SecondLastInst->getOperand(0));
186 FBB = LastInst->getOperand(0).getMBB();
187 return false;
188 }
189
190 // If the block ends with two NVPTX:GOTOs, handle it. The second one is not
191 // executed, so remove it.
192 if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
193 LastInst->getOpcode() == NVPTX::GOTO) {
194 TBB = SecondLastInst->getOperand(0).getMBB();
195 I = LastInst;
196 if (AllowModify)
197 I->eraseFromParent();
198 return false;
199 }
200
201 // Otherwise, can't handle this.
202 return true;
203 }
204
RemoveBranch(MachineBasicBlock & MBB) const205 unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
206 MachineBasicBlock::iterator I = MBB.end();
207 if (I == MBB.begin())
208 return 0;
209 --I;
210 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
211 return 0;
212
213 // Remove the branch.
214 I->eraseFromParent();
215
216 I = MBB.end();
217
218 if (I == MBB.begin())
219 return 1;
220 --I;
221 if (I->getOpcode() != NVPTX::CBranch)
222 return 1;
223
224 // Remove the branch.
225 I->eraseFromParent();
226 return 2;
227 }
228
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,DebugLoc DL) const229 unsigned NVPTXInstrInfo::InsertBranch(
230 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
231 ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
232 // Shouldn't be a fall through.
233 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
234 assert((Cond.size() == 1 || Cond.size() == 0) &&
235 "NVPTX branch conditions have two components!");
236
237 // One-way branch.
238 if (!FBB) {
239 if (Cond.empty()) // Unconditional branch
240 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
241 else // Conditional branch
242 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
243 .addMBB(TBB);
244 return 1;
245 }
246
247 // Two-way Conditional Branch.
248 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
249 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
250 return 2;
251 }
252