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Searched refs:sub0 (Results 1 – 25 of 32) sorted by relevance

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/external/vulkan-validation-layers/libs/glm/detail/
Dintrinsic_geometric.inl43 __m128 sub0 = _mm_sub_ps(p0, p1); local
44 __m128 len0 = sse_len_ps(sub0);
83 __m128 sub0 = _mm_sub_ps(mul0, mul1); local
84 return sub0;
118 __m128 sub0 = _mm_sub_ps(I, mul1); local
119 return sub0;
128 __m128 sub0 = _mm_sub_ps(glm::detail::one, mul0); local
130 __m128 mul2 = _mm_mul_ps(sub0, sub1);
Dintrinsic_common.inl179 __m128 sub0 = _mm_sub_ps(rnd0, and0); local
180 return sub0;
196 __m128 sub0 = _mm_sub_ps(add0, or0); local
197 return sub0;
206 __m128 sub0 = _mm_sub_ps(add0, or0); local
207 return sub0;
222 __m128 sub0 = _mm_sub_ps(x, flr0); local
223 return sub0;
231 __m128 sub0 = _mm_sub_ps(x, mul0); local
232 return sub0;
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td30 let SubRegIndices = [sub0, sub1];
40 let SubRegIndices = [sub0, sub1];
57 let SubRegIndices = [sub0, sub1];
91 def SGPR_64Regs : RegisterTuples<[sub0, sub1],
96 def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
103 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
114 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
138 def VGPR_64 : RegisterTuples<[sub0, sub1],
143 def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
149 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
[all …]
DSIMachineFunctionInfo.cpp115 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass); in addPrivateSegmentBuffer()
122 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass); in addDispatchPtr()
129 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass); in addQueuePtr()
136 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass); in addKernargSegmentPtr()
DSIInstrInfo.cpp323 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in copyPhysReg()
337 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in copyPhysReg()
347 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in copyPhysReg()
355 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, in copyPhysReg()
359 AMDGPU::sub0, AMDGPU::sub1, in copyPhysReg()
803 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
820 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
832 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
839 .addReg(RI.getSubReg(Src0, AMDGPU::sub0)) in expandPostRAPseudo()
840 .addReg(RI.getSubReg(Src1, AMDGPU::sub0)) in expandPostRAPseudo()
[all …]
DAMDGPURegisterInfo.cpp47 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4, in getSubRegFromChannel()
DR600Instructions.td479 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
485 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
1686 def : Extract_Element <f32, v4f32, 0, sub0>;
1691 def : Insert_Element <f32, v4f32, 0, sub0>;
1696 def : Extract_Element <i32, v4i32, 0, sub0>;
1701 def : Insert_Element <i32, v4i32, 0, sub0>;
1706 def : Extract_Element <f32, v2f32, 0, sub0>;
1709 def : Insert_Element <f32, v2f32, 0, sub0>;
1712 def : Extract_Element <i32, v2i32, 0, sub0>;
1715 def : Insert_Element <i32, v2i32, 0, sub0>;
DR600RegisterInfo.td23 let SubRegIndices = [sub0, sub1, sub2, sub3];
32 let SubRegIndices = [sub0, sub1];
DSIInstructions.td2150 (S_BCNT1_I32_B64 $src), sub0,
2627 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2628 sub0,
2647 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2648 sub0,
2657 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2658 sub0,
2721 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2724 0 /* clamp */, 0 /* omod */), sub0,
2725 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
[all …]
DSIFrameLowering.cpp190 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitPrologue()
DAMDGPUISelDAGToDAG.cpp418 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in Select()
451 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), in Select()
715 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectADD_SUB_I64()
1243 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32)); in SelectAddrSpaceCast()
1257 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), in SelectAddrSpaceCast()
/external/icu/android_icu4j/src/main/java/android/icu/util/
DLocaleData.java414 String sub0 = "{0}"; in getLocaleSeparator() local
418 int index0 = localeSeparator.indexOf(sub0); in getLocaleSeparator()
421 return localeSeparator.substring(index0 + sub0.length(), index1); in getLocaleSeparator()
/external/icu/icu4j/main/classes/core/src/com/ibm/icu/util/
DLocaleData.java442 String sub0 = "{0}"; in getLocaleSeparator() local
446 int index0 = localeSeparator.indexOf(sub0); in getLocaleSeparator()
449 return localeSeparator.substring(index0 + sub0.length(), index1); in getLocaleSeparator()
/external/lzma/CPP/7zip/Common/
DFilterCoder.h10 #define MY_QUERYINTERFACE_ENTRY_AG(i, sub0, sub) else if (iid == IID_ ## i) \ argument
11 { if (!sub) RINOK(sub0->QueryInterface(IID_ ## i, (void **)&sub)) \
/external/llvm/test/CodeGen/SystemZ/
Dfp-sub-01.ll106 %sub0 = fsub float %ret, %val0
107 %sub1 = fsub float %sub0, %val1
Dfp-sub-02.ll108 %sub0 = fsub double %ret, %val0
109 %sub1 = fsub double %sub0, %val1
Dint-sub-04.ll128 %sub0 = sub i64 %ret, %val0
129 %sub1 = sub i64 %sub0, %val1
Dint-sub-05.ll145 %sub0 = sub i128 %ret, %val0
146 %sub1 = sub i128 %sub0, %val1
Dint-sub-01.ll163 %sub0 = sub i32 %ret, %val0
164 %sub1 = sub i32 %sub0, %val1
Dint-sub-03.ll168 %sub0 = sub i64 %ret, %ext0
169 %sub1 = sub i64 %sub0, %ext1
Dint-sub-02.ll168 %sub0 = sub i64 %ret, %ext0
169 %sub1 = sub i64 %sub0, %ext1
/external/icu/icu4c/source/i18n/
Dulocdata.c335 static const UChar sub0[4] = { 0x007b, 0x0030, 0x007d , 0x0000 }; /* {0} */ in ulocdata_getLocaleSeparator() local
373 p0=u_strstr(separator, sub0); in ulocdata_getLocaleSeparator()
/external/libvpx/libvpx/vp8/common/mips/msa/
Dpostproc_msa.c589 v4i32 sub0, sub1, sub2, sub3; in vp8_mbpost_proc_across_ip_msa() local
620 UNPCK_SH_SW(sub_r, sub0, sub1); in vp8_mbpost_proc_across_ip_msa()
624 MUL4(sum0_w, sub0, sum1_w, sub1, sum2_w, sub2, sum3_w, sub3, in vp8_mbpost_proc_across_ip_msa()
694 v4i32 sub0, sub1, sub2, sub3, total0, total1, total2, total3; in vp8_mbpost_proc_down_msa() local
755 UNPCK_SH_SW(sub_r, sub0, sub1); in vp8_mbpost_proc_down_msa()
764 mul0 += add0 * sub0; in vp8_mbpost_proc_down_msa()
/external/opencv3/modules/viz/test/
Dtests_simple.cpp269 …std::vector<Affine3d> path = generate_test_trajectory<double>(), sub0, sub1, sub2, sub3, sub4, sub… in TEST()
272 Mat(path).rowRange(0, size/10+1).copyTo(sub0); in TEST()
282 viz.showWidget("sub0", WTrajectorySpheres(sub0, 0.25, 0.07)); in TEST()
/external/icu/icu4c/source/common/
Dlocdispnames.cpp469 static const UChar sub0[4] = { 0x007b, 0x0030, 0x007d , 0x0000 } ; /* {0} */ in uloc_getDisplayName() local
536 UChar *p0=u_strstr(separator, sub0); in uloc_getDisplayName()
553 UChar *p0=u_strstr(pattern, sub0); in uloc_getDisplayName()

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