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/external/boringssl/src/ssl/test/runner/curve25519/
Dfreeze_amd64.s21 MOVQ R12,8(SP)
37 MOVQ SI,R12
38 SHRQ $51,R12
40 ADDQ R12,DX
41 MOVQ DX,R12
42 SHRQ $51,R12
44 ADDQ R12,CX
45 MOVQ CX,R12
46 SHRQ $51,R12
48 ADDQ R12,R8
[all …]
Dladderstep_amd64.s21 MOVQ R12,8(SP)
35 MOVQ R8,R12
40 ADDQ ·_2P1234(SB),R12
50 SUBQ 104(DI),R12
60 MOVQ R12,120(SP)
79 MOVQ AX,R12
93 ADDQ AX,R12
132 ADDQ AX,R12
143 SHLQ $13,R13:R12
144 ANDQ DX,R12
[all …]
Dmul_amd64.s23 MOVQ R12,8(SP)
53 MOVQ AX,R12
69 ADDQ AX,R12
86 ADDQ AX,R12
120 ADDQ AX,R12
132 ADDQ AX,R12
144 SHLQ $13,R13:R12
145 ANDQ SI,R12
146 ADDQ R11,R12
161 ADDQ R12,DX
[all …]
Dsquare_amd64.s22 MOVQ R12,8(SP)
41 MOVQ DX,R12
55 ADCQ DX,R12
94 ADCQ DX,R12
106 SHLQ $13,R12:R11
111 ADDQ R12,R13
144 MOVQ 8(SP),R12
/external/boringssl/src/ssl/test/runner/poly1305/
Dpoly1305_arm.s28 MOVW R5>>8, R12
37 AND R12, R6, R6
67 MOVW R2, R12
76 CMP $16, R12
94 MOVW R2>>14, R12
99 ORR R3<<18, R12, R12
104 BIC $0xfc000000, R12, R12
110 ADD R12, R8, R8
114 MULLU R3, R5, (R14, R12)
116 MULALU R2, R6, (R14, R12)
[all …]
/external/opencv3/samples/cpp/
D3calibration.cpp54 Mat& R12, Mat& T12, Mat& R13, Mat& T13) in run3Calibration() argument
148 R12 = R; T12 = T; in run3Calibration()
247 Mat cameraMatrix[3], distCoeffs[3], R[3], P[3], R12, T12; in main() local
299 R12, T12, R13, T13); in main()
311 fs << "R12" << R12; in main()
325 imageSize, R12, T12, R13, T13, in main()
/external/llvm/test/CodeGen/PowerPC/
D2010-03-09-indirect-call.ll5 ; Indirect calls must use R12 on Darwin (i.e., R12 must contain the address of
/external/llvm/test/CodeGen/Mips/
Datomic.ll124 ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
126 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
164 ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
166 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
205 ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
207 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
284 ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
292 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
325 ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
333 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430CallingConv.td19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
DMSP430RegisterInfo.td61 def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
DMSP430RegisterInfo.cpp55 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
61 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
/external/libunwind/src/x86_64/
Dinit.h61 c->dwarf.loc[R12] = REG_INIT_LOC(c, r12, R12); in common_init()
DGget_save_loc.c43 case UNW_X86_64_R12: loc = c->dwarf.loc[R12]; break; in unw_get_save_loc()
Dunwind_i.h51 #define R12 12 macro
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s91 STMFD SP!,{R4-R12,LR}
145 @SUB R12,R8,R3, LSR #1 @// v offset
438 @ADD R2,R2,R12 @// adjust v pointer
448 LDMFD SP!,{R4-R12,PC}
/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h41 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
52 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
DThumbRegisterInfo.cpp462 .addReg(ARM::R12, RegState::Define) in saveScavengerRegister()
475 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) { in saveScavengerRegister()
483 if (MO.getReg() == ARM::R12) { in saveScavengerRegister()
492 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill)); in saveScavengerRegister()
/external/libgdx/extensions/gdx-bullet/jni/src/bullet/BulletCollision/CollisionDispatch/
DbtBoxBoxDetector.cpp271 btScalar A[3],B[3],R11,R12,R13,R21,R22,R23,R31,R32,R33, in dBoxBox2() local
288 R11 = dDOT44(R1+0,R2+0); R12 = dDOT44(R1+0,R2+1); R13 = dDOT44(R1+0,R2+2); in dBoxBox2()
292 Q11 = btFabs(R11); Q12 = btFabs(R12); Q13 = btFabs(R13); in dBoxBox2()
369 TST(pp[0]*R32-pp[2]*R12,(A[0]*Q32+A[2]*Q12+B[0]*Q23+B[2]*Q21),R32,0,-R12,11); in dBoxBox2()
374 TST(pp[1]*R12-pp[0]*R22,(A[0]*Q22+A[1]*Q12+B[0]*Q33+B[2]*Q31),-R22,R12,0,14); in dBoxBox2()
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td57 def R12 : AVRReg<12, "r12">, DwarfRegNum<[12]>;
100 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/external/llvm/test/CodeGen/ARM/
Dunaligned_load_store.ll18 ; EXPANDED: ldrb [[R12:r[0-9]+]]
21 ; EXPANDED: strb [[R12]]
/external/llvm/test/CodeGen/Thumb2/
D2010-08-10-VarSizedAllocaBug.ll10 ; CHECK: sub.w [[R12:r[0-9]+]], r4, #1000
11 ; CHECK: mov sp, [[R12]]
/external/strace/linux/x86_64/
Duserent.h4 XLAT(8*R12),
/external/llvm/lib/Transforms/InstCombine/
DInstCombineAndOrXor.cpp638 Value *R11,*R12; in foldLogOpOfMaskedICmpsHelper() local
640 if (decomposeBitTestICmp(RHS, RHSCC, R11, R12, R2)) { in foldLogOpOfMaskedICmpsHelper()
642 A = R11; D = R12; in foldLogOpOfMaskedICmpsHelper()
643 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in foldLogOpOfMaskedICmpsHelper()
644 A = R12; D = R11; in foldLogOpOfMaskedICmpsHelper()
650 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) { in foldLogOpOfMaskedICmpsHelper()
654 R12 = Constant::getAllOnesValue(R1->getType()); in foldLogOpOfMaskedICmpsHelper()
658 A = R11; D = R12; E = R2; ok = true; in foldLogOpOfMaskedICmpsHelper()
659 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in foldLogOpOfMaskedICmpsHelper()
660 A = R12; D = R11; E = R2; ok = true; in foldLogOpOfMaskedICmpsHelper()
[all …]
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h35 #define R12 24 macro
/external/valgrind/coregrind/m_sigframe/
Dsigframe-amd64-darwin.c97 SC2(__r12,R12); in synthesize_ucontext()
125 SC2(R12,__r12); in restore_from_ucontext()

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