1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __VMWGFX_DRM_H__ 20 #define __VMWGFX_DRM_H__ 21 #include <drm/drm.h> 22 #define DRM_VMW_MAX_SURFACE_FACES 6 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define DRM_VMW_MAX_MIP_LEVELS 24 25 #define DRM_VMW_GET_PARAM 0 26 #define DRM_VMW_ALLOC_DMABUF 1 27 #define DRM_VMW_UNREF_DMABUF 2 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define DRM_VMW_CURSOR_BYPASS 3 30 #define DRM_VMW_CONTROL_STREAM 4 31 #define DRM_VMW_CLAIM_STREAM 5 32 #define DRM_VMW_UNREF_STREAM 6 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define DRM_VMW_CREATE_CONTEXT 7 35 #define DRM_VMW_UNREF_CONTEXT 8 36 #define DRM_VMW_CREATE_SURFACE 9 37 #define DRM_VMW_UNREF_SURFACE 10 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define DRM_VMW_REF_SURFACE 11 40 #define DRM_VMW_EXECBUF 12 41 #define DRM_VMW_GET_3D_CAP 13 42 #define DRM_VMW_FENCE_WAIT 14 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define DRM_VMW_FENCE_SIGNALED 15 45 #define DRM_VMW_FENCE_UNREF 16 46 #define DRM_VMW_FENCE_EVENT 17 47 #define DRM_VMW_PRESENT 18 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define DRM_VMW_PRESENT_READBACK 19 50 #define DRM_VMW_UPDATE_LAYOUT 20 51 #define DRM_VMW_CREATE_SHADER 21 52 #define DRM_VMW_UNREF_SHADER 22 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define DRM_VMW_GB_SURFACE_CREATE 23 55 #define DRM_VMW_GB_SURFACE_REF 24 56 #define DRM_VMW_SYNCCPU 25 57 #define DRM_VMW_CREATE_EXTENDED_CONTEXT 26 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define DRM_VMW_PARAM_NUM_STREAMS 0 60 #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 61 #define DRM_VMW_PARAM_3D 2 62 #define DRM_VMW_PARAM_HW_CAPS 3 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define DRM_VMW_PARAM_FIFO_CAPS 4 65 #define DRM_VMW_PARAM_MAX_FB_SIZE 5 66 #define DRM_VMW_PARAM_FIFO_HW_VERSION 6 67 #define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define DRM_VMW_PARAM_3D_CAPS_SIZE 8 70 #define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 71 #define DRM_VMW_PARAM_MAX_MOB_SIZE 10 72 #define DRM_VMW_PARAM_SCREEN_TARGET 11 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define DRM_VMW_PARAM_DX 12 75 enum drm_vmw_handle_type { 76 DRM_VMW_HANDLE_LEGACY = 0, 77 DRM_VMW_HANDLE_PRIME = 1 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 }; 80 struct drm_vmw_getparam_arg { 81 uint64_t value; 82 uint32_t param; 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 uint32_t pad64; 85 }; 86 struct drm_vmw_context_arg { 87 int32_t cid; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 uint32_t pad64; 90 }; 91 struct drm_vmw_surface_create_req { 92 uint32_t flags; 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 uint32_t format; 95 uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES]; 96 uint64_t size_addr; 97 int32_t shareable; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 int32_t scanout; 100 }; 101 struct drm_vmw_surface_arg { 102 int32_t sid; 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 enum drm_vmw_handle_type handle_type; 105 }; 106 struct drm_vmw_size { 107 uint32_t width; 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 uint32_t height; 110 uint32_t depth; 111 uint32_t pad64; 112 }; 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 union drm_vmw_surface_create_arg { 115 struct drm_vmw_surface_arg rep; 116 struct drm_vmw_surface_create_req req; 117 }; 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 union drm_vmw_surface_reference_arg { 120 struct drm_vmw_surface_create_req rep; 121 struct drm_vmw_surface_arg req; 122 }; 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define DRM_VMW_EXECBUF_VERSION 2 125 struct drm_vmw_execbuf_arg { 126 uint64_t commands; 127 uint32_t command_size; 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 uint32_t throttle_us; 130 uint64_t fence_rep; 131 uint32_t version; 132 uint32_t flags; 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 uint32_t context_handle; 135 uint32_t pad64; 136 }; 137 struct drm_vmw_fence_rep { 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 uint32_t handle; 140 uint32_t mask; 141 uint32_t seqno; 142 uint32_t passed_seqno; 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 uint32_t pad64; 145 int32_t error; 146 }; 147 struct drm_vmw_alloc_dmabuf_req { 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 uint32_t size; 150 uint32_t pad64; 151 }; 152 struct drm_vmw_dmabuf_rep { 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 uint64_t map_handle; 155 uint32_t handle; 156 uint32_t cur_gmr_id; 157 uint32_t cur_gmr_offset; 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 uint32_t pad64; 160 }; 161 union drm_vmw_alloc_dmabuf_arg { 162 struct drm_vmw_alloc_dmabuf_req req; 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 struct drm_vmw_dmabuf_rep rep; 165 }; 166 struct drm_vmw_unref_dmabuf_arg { 167 uint32_t handle; 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 uint32_t pad64; 170 }; 171 struct drm_vmw_rect { 172 int32_t x; 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 int32_t y; 175 uint32_t w; 176 uint32_t h; 177 }; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 struct drm_vmw_control_stream_arg { 180 uint32_t stream_id; 181 uint32_t enabled; 182 uint32_t flags; 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 uint32_t color_key; 185 uint32_t handle; 186 uint32_t offset; 187 int32_t format; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 uint32_t size; 190 uint32_t width; 191 uint32_t height; 192 uint32_t pitch[3]; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 uint32_t pad64; 195 struct drm_vmw_rect src; 196 struct drm_vmw_rect dst; 197 }; 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 #define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) 200 #define DRM_VMW_CURSOR_BYPASS_FLAGS (1) 201 struct drm_vmw_cursor_bypass_arg { 202 uint32_t flags; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 uint32_t crtc_id; 205 int32_t xpos; 206 int32_t ypos; 207 int32_t xhot; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 int32_t yhot; 210 }; 211 struct drm_vmw_stream_arg { 212 uint32_t stream_id; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 uint32_t pad64; 215 }; 216 struct drm_vmw_get_3d_cap_arg { 217 uint64_t buffer; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 uint32_t max_size; 220 uint32_t pad64; 221 }; 222 #define DRM_VMW_FENCE_FLAG_EXEC (1 << 0) 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define DRM_VMW_FENCE_FLAG_QUERY (1 << 1) 225 #define DRM_VMW_WAIT_OPTION_UNREF (1 << 0) 226 struct drm_vmw_fence_wait_arg { 227 uint32_t handle; 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 int32_t cookie_valid; 230 uint64_t kernel_cookie; 231 uint64_t timeout_us; 232 int32_t lazy; 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 int32_t flags; 235 int32_t wait_options; 236 int32_t pad64; 237 }; 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 struct drm_vmw_fence_signaled_arg { 240 uint32_t handle; 241 uint32_t flags; 242 int32_t signaled; 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 uint32_t passed_seqno; 245 uint32_t signaled_flags; 246 uint32_t pad64; 247 }; 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 struct drm_vmw_fence_arg { 250 uint32_t handle; 251 uint32_t pad64; 252 }; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 255 struct drm_vmw_event_fence { 256 struct drm_event base; 257 uint64_t user_data; 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 uint32_t tv_sec; 260 uint32_t tv_usec; 261 }; 262 #define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0) 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 struct drm_vmw_fence_event_arg { 265 uint64_t fence_rep; 266 uint64_t user_data; 267 uint32_t handle; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 uint32_t flags; 270 }; 271 struct drm_vmw_present_arg { 272 uint32_t fb_id; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 uint32_t sid; 275 int32_t dest_x; 276 int32_t dest_y; 277 uint64_t clips_ptr; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 uint32_t num_clips; 280 uint32_t pad64; 281 }; 282 struct drm_vmw_present_readback_arg { 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 uint32_t fb_id; 285 uint32_t num_clips; 286 uint64_t clips_ptr; 287 uint64_t fence_rep; 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 }; 290 struct drm_vmw_update_layout_arg { 291 uint32_t num_outputs; 292 uint32_t pad64; 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 uint64_t rects; 295 }; 296 enum drm_vmw_shader_type { 297 drm_vmw_shader_type_vs = 0, 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 drm_vmw_shader_type_ps, 300 }; 301 struct drm_vmw_shader_create_arg { 302 enum drm_vmw_shader_type shader_type; 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 uint32_t size; 305 uint32_t buffer_handle; 306 uint32_t shader_handle; 307 uint64_t offset; 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 }; 310 struct drm_vmw_shader_arg { 311 uint32_t handle; 312 uint32_t pad64; 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 }; 315 enum drm_vmw_surface_flags { 316 drm_vmw_surface_flag_shareable = (1 << 0), 317 drm_vmw_surface_flag_scanout = (1 << 1), 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 drm_vmw_surface_flag_create_buffer = (1 << 2) 320 }; 321 struct drm_vmw_gb_surface_create_req { 322 uint32_t svga3d_flags; 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 uint32_t format; 325 uint32_t mip_levels; 326 enum drm_vmw_surface_flags drm_surface_flags; 327 uint32_t multisample_count; 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 uint32_t autogen_filter; 330 uint32_t buffer_handle; 331 uint32_t array_size; 332 struct drm_vmw_size base_size; 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 }; 335 struct drm_vmw_gb_surface_create_rep { 336 uint32_t handle; 337 uint32_t backup_size; 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 uint32_t buffer_handle; 340 uint32_t buffer_size; 341 uint64_t buffer_map_handle; 342 }; 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 union drm_vmw_gb_surface_create_arg { 345 struct drm_vmw_gb_surface_create_rep rep; 346 struct drm_vmw_gb_surface_create_req req; 347 }; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 struct drm_vmw_gb_surface_ref_rep { 350 struct drm_vmw_gb_surface_create_req creq; 351 struct drm_vmw_gb_surface_create_rep crep; 352 }; 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 union drm_vmw_gb_surface_reference_arg { 355 struct drm_vmw_gb_surface_ref_rep rep; 356 struct drm_vmw_surface_arg req; 357 }; 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 enum drm_vmw_synccpu_flags { 360 drm_vmw_synccpu_read = (1 << 0), 361 drm_vmw_synccpu_write = (1 << 1), 362 drm_vmw_synccpu_dontblock = (1 << 2), 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 drm_vmw_synccpu_allow_cs = (1 << 3) 365 }; 366 enum drm_vmw_synccpu_op { 367 drm_vmw_synccpu_grab, 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 drm_vmw_synccpu_release 370 }; 371 struct drm_vmw_synccpu_arg { 372 enum drm_vmw_synccpu_op op; 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 enum drm_vmw_synccpu_flags flags; 375 uint32_t handle; 376 uint32_t pad64; 377 }; 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 enum drm_vmw_extended_context { 380 drm_vmw_context_legacy, 381 drm_vmw_context_dx 382 }; 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 union drm_vmw_extended_context_arg { 385 enum drm_vmw_extended_context req; 386 struct drm_vmw_context_arg rep; 387 }; 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 #endif 390