1//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the top level entry point for the Hexagon target. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Target-independent interfaces which we are implementing 16//===----------------------------------------------------------------------===// 17 18include "llvm/Target/Target.td" 19 20//===----------------------------------------------------------------------===// 21// Hexagon Subtarget features. 22//===----------------------------------------------------------------------===// 23 24// Hexagon Architectures 25def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Hexagon V4">; 26def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Hexagon V5">; 27def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Hexagon V55">; 28def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">; 29 30// Hexagon ISA Extensions 31def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", 32 "true", "Hexagon HVX instructions">; 33def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", 34 "true", "Hexagon HVX Double instructions">; 35 36//===----------------------------------------------------------------------===// 37// Hexagon Instruction Predicate Definitions. 38//===----------------------------------------------------------------------===// 39def HasV5T : Predicate<"HST->hasV5TOps()">; 40def NoV5T : Predicate<"!HST->hasV5TOps()">; 41def HasV55T : Predicate<"HST->hasV55TOps()">, 42 AssemblerPredicate<"ArchV55">; 43def HasV60T : Predicate<"HST->hasV60TOps()">, 44 AssemblerPredicate<"ArchV60">; 45def UseMEMOP : Predicate<"HST->useMemOps()">; 46def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; 47def UseHVXDbl : Predicate<"HST->useHVXDblOps()">, 48 AssemblerPredicate<"ExtensionHVXDbl">; 49def UseHVXSgl : Predicate<"HST->useHVXSglOps()">; 50 51def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">, 52 AssemblerPredicate<"ExtensionHVX">; 53 54//===----------------------------------------------------------------------===// 55// Classes used for relation maps. 56//===----------------------------------------------------------------------===// 57 58class ImmRegShl; 59// PredRel - Filter class used to relate non-predicated instructions with their 60// predicated forms. 61class PredRel; 62// PredNewRel - Filter class used to relate predicated instructions with their 63// predicate-new forms. 64class PredNewRel: PredRel; 65// ImmRegRel - Filter class used to relate instructions having reg-reg form 66// with their reg-imm counterparts. 67class ImmRegRel; 68// NewValueRel - Filter class used to relate regular store instructions with 69// their new-value store form. 70class NewValueRel: PredNewRel; 71// NewValueRel - Filter class used to relate load/store instructions having 72// different addressing modes with each other. 73class AddrModeRel: NewValueRel; 74class IntrinsicsRel; 75 76//===----------------------------------------------------------------------===// 77// Generate mapping table to relate non-predicate instructions with their 78// predicated formats - true and false. 79// 80 81def getPredOpcode : InstrMapping { 82 let FilterClass = "PredRel"; 83 // Instructions with the same BaseOpcode and isNVStore values form a row. 84 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"]; 85 // Instructions with the same predicate sense form a column. 86 let ColFields = ["PredSense"]; 87 // The key column is the unpredicated instructions. 88 let KeyCol = [""]; 89 // Value columns are PredSense=true and PredSense=false 90 let ValueCols = [["true"], ["false"]]; 91} 92 93//===----------------------------------------------------------------------===// 94// Generate mapping table to relate predicate-true instructions with their 95// predicate-false forms 96// 97def getFalsePredOpcode : InstrMapping { 98 let FilterClass = "PredRel"; 99 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"]; 100 let ColFields = ["PredSense"]; 101 let KeyCol = ["true"]; 102 let ValueCols = [["false"]]; 103} 104 105//===----------------------------------------------------------------------===// 106// Generate mapping table to relate predicate-false instructions with their 107// predicate-true forms 108// 109def getTruePredOpcode : InstrMapping { 110 let FilterClass = "PredRel"; 111 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"]; 112 let ColFields = ["PredSense"]; 113 let KeyCol = ["false"]; 114 let ValueCols = [["true"]]; 115} 116 117//===----------------------------------------------------------------------===// 118// Generate mapping table to relate predicated instructions with their .new 119// format. 120// 121def getPredNewOpcode : InstrMapping { 122 let FilterClass = "PredNewRel"; 123 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; 124 let ColFields = ["PNewValue"]; 125 let KeyCol = [""]; 126 let ValueCols = [["new"]]; 127} 128 129//===----------------------------------------------------------------------===// 130// Generate mapping table to relate .new predicated instructions with their old 131// format. 132// 133def getPredOldOpcode : InstrMapping { 134 let FilterClass = "PredNewRel"; 135 let RowFields = ["BaseOpcode", "PredSense", "isNVStore"]; 136 let ColFields = ["PNewValue"]; 137 let KeyCol = ["new"]; 138 let ValueCols = [[""]]; 139} 140 141//===----------------------------------------------------------------------===// 142// Generate mapping table to relate store instructions with their new-value 143// format. 144// 145def getNewValueOpcode : InstrMapping { 146 let FilterClass = "NewValueRel"; 147 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"]; 148 let ColFields = ["NValueST"]; 149 let KeyCol = ["false"]; 150 let ValueCols = [["true"]]; 151} 152 153//===----------------------------------------------------------------------===// 154// Generate mapping table to relate new-value store instructions with their old 155// format. 156// 157def getNonNVStore : InstrMapping { 158 let FilterClass = "NewValueRel"; 159 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"]; 160 let ColFields = ["NValueST"]; 161 let KeyCol = ["true"]; 162 let ValueCols = [["false"]]; 163} 164 165def getBaseWithImmOffset : InstrMapping { 166 let FilterClass = "AddrModeRel"; 167 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", 168 "isFloat"]; 169 let ColFields = ["addrMode"]; 170 let KeyCol = ["Absolute"]; 171 let ValueCols = [["BaseImmOffset"]]; 172} 173 174def getBaseWithRegOffset : InstrMapping { 175 let FilterClass = "AddrModeRel"; 176 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 177 let ColFields = ["addrMode"]; 178 let KeyCol = ["BaseImmOffset"]; 179 let ValueCols = [["BaseRegOffset"]]; 180} 181 182def getRegForm : InstrMapping { 183 let FilterClass = "ImmRegRel"; 184 let RowFields = ["CextOpcode", "PredSense", "PNewValue"]; 185 let ColFields = ["InputType"]; 186 let KeyCol = ["imm"]; 187 let ValueCols = [["reg"]]; 188} 189 190def getRegShlForm : InstrMapping { 191 let FilterClass = "ImmRegShl"; 192 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 193 let ColFields = ["InputType"]; 194 let KeyCol = ["imm"]; 195 let ValueCols = [["reg"]]; 196} 197 198def notTakenBranchPrediction : InstrMapping { 199 let FilterClass = "PredRel"; 200 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"]; 201 let ColFields = ["isBrTaken"]; 202 let KeyCol = ["true"]; 203 let ValueCols = [["false"]]; 204} 205 206def takenBranchPrediction : InstrMapping { 207 let FilterClass = "PredRel"; 208 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"]; 209 let ColFields = ["isBrTaken"]; 210 let KeyCol = ["false"]; 211 let ValueCols = [["true"]]; 212} 213 214def getRealHWInstr : InstrMapping { 215 let FilterClass = "IntrinsicsRel"; 216 let RowFields = ["BaseOpcode"]; 217 let ColFields = ["InstrType"]; 218 let KeyCol = ["Pseudo"]; 219 let ValueCols = [["Pseudo"], ["Real"]]; 220} 221//===----------------------------------------------------------------------===// 222// Register File, Calling Conv, Instruction Descriptions 223//===----------------------------------------------------------------------===// 224include "HexagonSchedule.td" 225include "HexagonRegisterInfo.td" 226include "HexagonCallingConv.td" 227include "HexagonInstrInfo.td" 228include "HexagonIntrinsics.td" 229include "HexagonIntrinsicsDerived.td" 230 231def HexagonInstrInfo : InstrInfo; 232 233//===----------------------------------------------------------------------===// 234// Hexagon processors supported. 235//===----------------------------------------------------------------------===// 236 237class Proc<string Name, SchedMachineModel Model, 238 list<SubtargetFeature> Features> 239 : ProcessorModel<Name, Model, Features>; 240 241def : Proc<"hexagonv4", HexagonModelV4, 242 [ArchV4]>; 243def : Proc<"hexagonv5", HexagonModelV4, 244 [ArchV4, ArchV5]>; 245def : Proc<"hexagonv55", HexagonModelV55, 246 [ArchV4, ArchV5, ArchV55]>; 247def : Proc<"hexagonv60", HexagonModelV60, 248 [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>; 249 250//===----------------------------------------------------------------------===// 251// Declare the target which we are implementing 252//===----------------------------------------------------------------------===// 253 254def HexagonAsmParserVariant : AsmParserVariant { 255 int Variant = 0; 256 string TokenizingCharacters = "#()=:.<>!+*"; 257} 258 259def Hexagon : Target { 260 // Pull in Instruction Info: 261 let InstructionSet = HexagonInstrInfo; 262 let AssemblyParserVariants = [HexagonAsmParserVariant]; 263} 264