1 //===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Sparc implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H 15 #define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H 16 17 #include "SparcRegisterInfo.h" 18 #include "llvm/Target/TargetInstrInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "SparcGenInstrInfo.inc" 22 23 namespace llvm { 24 25 class SparcSubtarget; 26 27 /// SPII - This namespace holds all of the target specific flags that 28 /// instruction info tracks. 29 /// 30 namespace SPII { 31 enum { 32 Pseudo = (1<<0), 33 Load = (1<<1), 34 Store = (1<<2), 35 DelaySlot = (1<<3) 36 }; 37 } 38 39 class SparcInstrInfo : public SparcGenInstrInfo { 40 const SparcRegisterInfo RI; 41 const SparcSubtarget& Subtarget; 42 virtual void anchor(); 43 public: 44 explicit SparcInstrInfo(SparcSubtarget &ST); 45 46 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 47 /// such, whenever a client has an instance of instruction info, it should 48 /// always be able to get register info as well (through this method). 49 /// getRegisterInfo()50 const SparcRegisterInfo &getRegisterInfo() const { return RI; } 51 52 /// isLoadFromStackSlot - If the specified machine instruction is a direct 53 /// load from a stack slot, return the virtual or physical register number of 54 /// the destination along with the FrameIndex of the loaded stack slot. If 55 /// not, return 0. This predicate must return 0 if the instruction has 56 /// any side effects other than loading from the stack slot. 57 unsigned isLoadFromStackSlot(const MachineInstr *MI, 58 int &FrameIndex) const override; 59 60 /// isStoreToStackSlot - If the specified machine instruction is a direct 61 /// store to a stack slot, return the virtual or physical register number of 62 /// the source reg along with the FrameIndex of the loaded stack slot. If 63 /// not, return 0. This predicate must return 0 if the instruction has 64 /// any side effects other than storing to the stack slot. 65 unsigned isStoreToStackSlot(const MachineInstr *MI, 66 int &FrameIndex) const override; 67 68 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 69 MachineBasicBlock *&FBB, 70 SmallVectorImpl<MachineOperand> &Cond, 71 bool AllowModify = false) const override ; 72 73 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 74 75 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 76 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 77 DebugLoc DL) const override; 78 79 void copyPhysReg(MachineBasicBlock &MBB, 80 MachineBasicBlock::iterator I, DebugLoc DL, 81 unsigned DestReg, unsigned SrcReg, 82 bool KillSrc) const override; 83 84 void storeRegToStackSlot(MachineBasicBlock &MBB, 85 MachineBasicBlock::iterator MBBI, 86 unsigned SrcReg, bool isKill, int FrameIndex, 87 const TargetRegisterClass *RC, 88 const TargetRegisterInfo *TRI) const override; 89 90 void loadRegFromStackSlot(MachineBasicBlock &MBB, 91 MachineBasicBlock::iterator MBBI, 92 unsigned DestReg, int FrameIndex, 93 const TargetRegisterClass *RC, 94 const TargetRegisterInfo *TRI) const override; 95 96 unsigned getGlobalBaseReg(MachineFunction *MF) const; 97 }; 98 99 } 100 101 #endif 102