1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4;CHECK-LABEL: {{^}}sample: 5;CHECK: s_wqm 6;CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 7define void @sample() #0 { 8main_body: 9 %r = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 10 %r0 = extractelement <4 x float> %r, i32 0 11 %r1 = extractelement <4 x float> %r, i32 1 12 %r2 = extractelement <4 x float> %r, i32 2 13 %r3 = extractelement <4 x float> %r, i32 3 14 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 15 ret void 16} 17 18;CHECK-LABEL: {{^}}sample_cl: 19;CHECK: s_wqm 20;CHECK: image_sample_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 21define void @sample_cl() #0 { 22main_body: 23 %r = call <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 24 %r0 = extractelement <4 x float> %r, i32 0 25 %r1 = extractelement <4 x float> %r, i32 1 26 %r2 = extractelement <4 x float> %r, i32 2 27 %r3 = extractelement <4 x float> %r, i32 3 28 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 29 ret void 30} 31 32;CHECK-LABEL: {{^}}sample_d: 33;CHECK-NOT: s_wqm 34;CHECK: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 35define void @sample_d() #0 { 36main_body: 37 %r = call <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 38 %r0 = extractelement <4 x float> %r, i32 0 39 %r1 = extractelement <4 x float> %r, i32 1 40 %r2 = extractelement <4 x float> %r, i32 2 41 %r3 = extractelement <4 x float> %r, i32 3 42 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 43 ret void 44} 45 46;CHECK-LABEL: {{^}}sample_d_cl: 47;CHECK-NOT: s_wqm 48;CHECK: image_sample_d_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 49define void @sample_d_cl() #0 { 50main_body: 51 %r = call <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 52 %r0 = extractelement <4 x float> %r, i32 0 53 %r1 = extractelement <4 x float> %r, i32 1 54 %r2 = extractelement <4 x float> %r, i32 2 55 %r3 = extractelement <4 x float> %r, i32 3 56 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 57 ret void 58} 59 60;CHECK-LABEL: {{^}}sample_l: 61;CHECK-NOT: s_wqm 62;CHECK: image_sample_l {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 63define void @sample_l() #0 { 64main_body: 65 %r = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 66 %r0 = extractelement <4 x float> %r, i32 0 67 %r1 = extractelement <4 x float> %r, i32 1 68 %r2 = extractelement <4 x float> %r, i32 2 69 %r3 = extractelement <4 x float> %r, i32 3 70 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 71 ret void 72} 73 74;CHECK-LABEL: {{^}}sample_b: 75;CHECK: s_wqm 76;CHECK: image_sample_b {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 77define void @sample_b() #0 { 78main_body: 79 %r = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 80 %r0 = extractelement <4 x float> %r, i32 0 81 %r1 = extractelement <4 x float> %r, i32 1 82 %r2 = extractelement <4 x float> %r, i32 2 83 %r3 = extractelement <4 x float> %r, i32 3 84 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 85 ret void 86} 87 88;CHECK-LABEL: {{^}}sample_b_cl: 89;CHECK: s_wqm 90;CHECK: image_sample_b_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 91define void @sample_b_cl() #0 { 92main_body: 93 %r = call <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 94 %r0 = extractelement <4 x float> %r, i32 0 95 %r1 = extractelement <4 x float> %r, i32 1 96 %r2 = extractelement <4 x float> %r, i32 2 97 %r3 = extractelement <4 x float> %r, i32 3 98 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 99 ret void 100} 101 102;CHECK-LABEL: {{^}}sample_lz: 103;CHECK-NOT: s_wqm 104;CHECK: image_sample_lz {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 105define void @sample_lz() #0 { 106main_body: 107 %r = call <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 108 %r0 = extractelement <4 x float> %r, i32 0 109 %r1 = extractelement <4 x float> %r, i32 1 110 %r2 = extractelement <4 x float> %r, i32 2 111 %r3 = extractelement <4 x float> %r, i32 3 112 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 113 ret void 114} 115 116;CHECK-LABEL: {{^}}sample_cd: 117;CHECK-NOT: s_wqm 118;CHECK: image_sample_cd {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 119define void @sample_cd() #0 { 120main_body: 121 %r = call <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 122 %r0 = extractelement <4 x float> %r, i32 0 123 %r1 = extractelement <4 x float> %r, i32 1 124 %r2 = extractelement <4 x float> %r, i32 2 125 %r3 = extractelement <4 x float> %r, i32 3 126 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 127 ret void 128} 129 130;CHECK-LABEL: {{^}}sample_cd_cl: 131;CHECK-NOT: s_wqm 132;CHECK: image_sample_cd_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 133define void @sample_cd_cl() #0 { 134main_body: 135 %r = call <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 136 %r0 = extractelement <4 x float> %r, i32 0 137 %r1 = extractelement <4 x float> %r, i32 1 138 %r2 = extractelement <4 x float> %r, i32 2 139 %r3 = extractelement <4 x float> %r, i32 3 140 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 141 ret void 142} 143 144;CHECK-LABEL: {{^}}sample_c: 145;CHECK: s_wqm 146;CHECK: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 147define void @sample_c() #0 { 148main_body: 149 %r = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 150 %r0 = extractelement <4 x float> %r, i32 0 151 %r1 = extractelement <4 x float> %r, i32 1 152 %r2 = extractelement <4 x float> %r, i32 2 153 %r3 = extractelement <4 x float> %r, i32 3 154 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 155 ret void 156} 157 158;CHECK-LABEL: {{^}}sample_c_cl: 159;CHECK: s_wqm 160;CHECK: image_sample_c_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 161define void @sample_c_cl() #0 { 162main_body: 163 %r = call <4 x float> @llvm.SI.image.sample.c.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 164 %r0 = extractelement <4 x float> %r, i32 0 165 %r1 = extractelement <4 x float> %r, i32 1 166 %r2 = extractelement <4 x float> %r, i32 2 167 %r3 = extractelement <4 x float> %r, i32 3 168 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 169 ret void 170} 171 172;CHECK-LABEL: {{^}}sample_c_d: 173;CHECK-NOT: s_wqm 174;CHECK: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 175define void @sample_c_d() #0 { 176main_body: 177 %r = call <4 x float> @llvm.SI.image.sample.c.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 178 %r0 = extractelement <4 x float> %r, i32 0 179 %r1 = extractelement <4 x float> %r, i32 1 180 %r2 = extractelement <4 x float> %r, i32 2 181 %r3 = extractelement <4 x float> %r, i32 3 182 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 183 ret void 184} 185 186;CHECK-LABEL: {{^}}sample_c_d_cl: 187;CHECK-NOT: s_wqm 188;CHECK: image_sample_c_d_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 189define void @sample_c_d_cl() #0 { 190main_body: 191 %r = call <4 x float> @llvm.SI.image.sample.c.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 192 %r0 = extractelement <4 x float> %r, i32 0 193 %r1 = extractelement <4 x float> %r, i32 1 194 %r2 = extractelement <4 x float> %r, i32 2 195 %r3 = extractelement <4 x float> %r, i32 3 196 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 197 ret void 198} 199 200;CHECK-LABEL: {{^}}sample_c_l: 201;CHECK-NOT: s_wqm 202;CHECK: image_sample_c_l {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 203define void @sample_c_l() #0 { 204main_body: 205 %r = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 206 %r0 = extractelement <4 x float> %r, i32 0 207 %r1 = extractelement <4 x float> %r, i32 1 208 %r2 = extractelement <4 x float> %r, i32 2 209 %r3 = extractelement <4 x float> %r, i32 3 210 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 211 ret void 212} 213 214;CHECK-LABEL: {{^}}sample_c_b: 215;CHECK: s_wqm 216;CHECK: image_sample_c_b {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 217define void @sample_c_b() #0 { 218main_body: 219 %r = call <4 x float> @llvm.SI.image.sample.c.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 220 %r0 = extractelement <4 x float> %r, i32 0 221 %r1 = extractelement <4 x float> %r, i32 1 222 %r2 = extractelement <4 x float> %r, i32 2 223 %r3 = extractelement <4 x float> %r, i32 3 224 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 225 ret void 226} 227 228;CHECK-LABEL: {{^}}sample_c_b_cl: 229;CHECK: s_wqm 230;CHECK: image_sample_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 231define void @sample_c_b_cl() #0 { 232main_body: 233 %r = call <4 x float> @llvm.SI.image.sample.c.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 234 %r0 = extractelement <4 x float> %r, i32 0 235 %r1 = extractelement <4 x float> %r, i32 1 236 %r2 = extractelement <4 x float> %r, i32 2 237 %r3 = extractelement <4 x float> %r, i32 3 238 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 239 ret void 240} 241 242;CHECK-LABEL: {{^}}sample_c_lz: 243;CHECK-NOT: s_wqm 244;CHECK: image_sample_c_lz {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 245define void @sample_c_lz() #0 { 246main_body: 247 %r = call <4 x float> @llvm.SI.image.sample.c.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 248 %r0 = extractelement <4 x float> %r, i32 0 249 %r1 = extractelement <4 x float> %r, i32 1 250 %r2 = extractelement <4 x float> %r, i32 2 251 %r3 = extractelement <4 x float> %r, i32 3 252 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 253 ret void 254} 255 256;CHECK-LABEL: {{^}}sample_c_cd: 257;CHECK-NOT: s_wqm 258;CHECK: image_sample_c_cd {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 259define void @sample_c_cd() #0 { 260main_body: 261 %r = call <4 x float> @llvm.SI.image.sample.c.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 262 %r0 = extractelement <4 x float> %r, i32 0 263 %r1 = extractelement <4 x float> %r, i32 1 264 %r2 = extractelement <4 x float> %r, i32 2 265 %r3 = extractelement <4 x float> %r, i32 3 266 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 267 ret void 268} 269 270;CHECK-LABEL: {{^}}sample_c_cd_cl: 271;CHECK-NOT: s_wqm 272;CHECK: image_sample_c_cd_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 273define void @sample_c_cd_cl() #0 { 274main_body: 275 %r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 276 %r0 = extractelement <4 x float> %r, i32 0 277 %r1 = extractelement <4 x float> %r, i32 1 278 %r2 = extractelement <4 x float> %r, i32 2 279 %r3 = extractelement <4 x float> %r, i32 3 280 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 281 ret void 282} 283 284 285declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 286declare <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 287declare <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 288declare <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 289declare <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 290declare <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 291declare <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 292declare <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 293declare <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 294declare <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 295 296declare <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 297declare <4 x float> @llvm.SI.image.sample.c.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 298declare <4 x float> @llvm.SI.image.sample.c.d.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 299declare <4 x float> @llvm.SI.image.sample.c.d.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 300declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 301declare <4 x float> @llvm.SI.image.sample.c.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 302declare <4 x float> @llvm.SI.image.sample.c.b.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 303declare <4 x float> @llvm.SI.image.sample.c.lz.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 304declare <4 x float> @llvm.SI.image.sample.c.cd.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 305declare <4 x float> @llvm.SI.image.sample.c.cd.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 306 307declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 308 309attributes #0 = { "ShaderType"="0" } 310attributes #1 = { nounwind readnone } 311