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1; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
2; RUN:      -fast-isel-abort=1 | FileCheck %s
3; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
4; RUN:      -fast-isel-abort=1 | FileCheck %s
5
6@sj = global i32 200, align 4
7@sk = global i32 -47, align 4
8@uj = global i32 200, align 4
9@uk = global i32 43, align 4
10@si = common global i32 0, align 4
11@ui = common global i32 0, align 4
12
13define void @rems() {
14  ; CHECK-LABEL:  rems:
15
16  ; CHECK:            lui     $[[GOT1:[0-9]+]], %hi(_gp_disp)
17  ; CHECK:            addiu   $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
18  ; CHECK:            addu    $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
19  ; CHECK-DAG:        lw      $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]])
20  ; CHECK-DAG:        lw      $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]])
21  ; CHECK-DAG:        lw      $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]])
22  ; CHECK-DAG:        lw      $[[J:[0-9]+]], 0($[[J_ADDR]])
23  ; CHECK-DAG:        lw      $[[K:[0-9]+]], 0($[[K_ADDR]])
24  ; CHECK-DAG:        div     $zero, $[[J]], $[[K]]
25  ; CHECK_DAG:        teq     $[[K]], $zero, 7
26  ; CHECK-DAG:        mfhi    $[[RESULT:[0-9]+]]
27  ; CHECK:            sw      $[[RESULT]], 0($[[I_ADDR]])
28  %1 = load i32, i32* @sj, align 4
29  %2 = load i32, i32* @sk, align 4
30  %rem = srem i32 %1, %2
31  store i32 %rem, i32* @si, align 4
32  ret void
33}
34
35; Function Attrs: noinline nounwind
36define void @remu() {
37  ; CHECK-LABEL:  remu:
38
39  ; CHECK:            lui     $[[GOT1:[0-9]+]], %hi(_gp_disp)
40  ; CHECK:            addiu   $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
41  ; CHECK:            addu    $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
42  ; CHECK-DAG:        lw      $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]])
43  ; CHECK-DAG:        lw      $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]])
44  ; CHECK-DAG:        lw      $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]])
45  ; CHECK-DAG:        lw      $[[J:[0-9]+]], 0($[[J_ADDR]])
46  ; CHECK-DAG:        lw      $[[K:[0-9]+]], 0($[[K_ADDR]])
47  ; CHECK-DAG:        divu    $zero, $[[J]], $[[K]]
48  ; CHECK_DAG:        teq     $[[K]], $zero, 7
49  ; CHECK-DAG:        mfhi    $[[RESULT:[0-9]+]]
50  ; CHECK:            sw      $[[RESULT]], 0($[[I_ADDR]])
51  %1 = load i32, i32* @uj, align 4
52  %2 = load i32, i32* @uk, align 4
53  %rem = urem i32 %1, %2
54  store i32 %rem, i32* @ui, align 4
55  ret void
56}
57