1; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 2; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 3; RUN: llc < %s -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 | FileCheck %s -check-prefix=MIPS16 4 5define i32 @bswap32(i32 signext %x) nounwind readnone { 6entry: 7; MIPS32-LABEL: bswap32: 8; MIPS32: wsbh $[[R0:[0-9]+]] 9; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 10 11; MIPS64-LABEL: bswap32: 12; MIPS64: wsbh $[[R0:[0-9]+]] 13; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16 14 15; MIPS16-LABEL: bswap32: 16; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8 17; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24 18; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8 19; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24 20; MIPS16-DAG: li $[[R4:[0-9]+]], 65280 21; MIPS16-DAG: and $[[R4]], $[[R0]] 22; MIPS16-DAG: or $[[R1]], $[[R4]] 23; MIPS16-DAG: lw $[[R7:[0-9]+]], $CPI 24; MIPS16-DAG: and $[[R7]], $[[R2]] 25; MIPS16-DAG: or $[[R3]], $[[R7]] 26; MIPS16-DAG: or $[[R3]], $[[R1]] 27 28 %or.3 = call i32 @llvm.bswap.i32(i32 %x) 29 ret i32 %or.3 30} 31 32define i64 @bswap64(i64 signext %x) nounwind readnone { 33entry: 34; MIPS32-LABEL: bswap64: 35; MIPS32: wsbh $[[R0:[0-9]+]] 36; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 37; MIPS32: wsbh $[[R0:[0-9]+]] 38; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 39 40; MIPS64-LABEL: bswap64: 41; MIPS64: dsbh $[[R0:[0-9]+]] 42; MIPS64: dshd ${{[0-9]+}}, $[[R0]] 43 44; MIPS16-LABEL: bswap64: 45; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 8 46; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 24 47; MIPS16-DAG: sll $[[R2:[0-9]+]], $5, 8 48; MIPS16-DAG: sll $[[R3:[0-9]+]], $5, 24 49; MIPS16-DAG: li $[[R4:[0-9]+]], 65280 50; MIPS16-DAG: and $[[R0]], $[[R4]] 51; MIPS16-DAG: or $[[R1]], $[[R0]] 52; MIPS16-DAG: lw $[[R7:[0-9]+]], 1f 53; MIPS16-DAG: and $[[R2]], $[[R7]] 54; MIPS16-DAG: or $[[R3]], $[[R2]] 55; MIPS16-DAG: or $[[R3]], $[[R1]] 56; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8 57; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24 58; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8 59; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24 60; MIPS16-DAG: li $[[R4:[0-9]+]], 65280 61; MIPS16-DAG: and $[[R0]], $[[R4]] 62; MIPS16-DAG: or $[[R1]], $[[R0]] 63; MIPS16-DAG: lw $[[R7:[0-9]+]], 1f 64; MIPS16-DAG: and $[[R2]], $[[R7]] 65; MIPS16-DAG: or $[[R3]], $[[R2]] 66; MIPS16-DAG: or $[[R3]], $[[R1]] 67 68 %or.7 = call i64 @llvm.bswap.i64(i64 %x) 69 ret i64 %or.7 70} 71 72define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone { 73entry: 74; MIPS32-LABEL: bswapv4i32: 75; MIPS32-DAG: wsbh $[[R0:[0-9]+]] 76; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 77; MIPS32-DAG: wsbh $[[R0:[0-9]+]] 78; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 79; MIPS32-DAG: wsbh $[[R0:[0-9]+]] 80; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 81; MIPS32-DAG: wsbh $[[R0:[0-9]+]] 82; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 83 84; MIPS64-LABEL: bswapv4i32: 85; MIPS64-DAG: wsbh $[[R0:[0-9]+]] 86; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 87; MIPS64-DAG: wsbh $[[R0:[0-9]+]] 88; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 89; MIPS64-DAG: wsbh $[[R0:[0-9]+]] 90; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 91; MIPS64-DAG: wsbh $[[R0:[0-9]+]] 92; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 93 94; Don't bother with a MIPS16 version. It's just bswap32 repeated four times and 95; would be very long 96 97 %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %x) 98 ret <4 x i32> %ret 99} 100 101declare i32 @llvm.bswap.i32(i32) nounwind readnone 102 103declare i64 @llvm.bswap.i64(i64) nounwind readnone 104 105declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone 106