1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ 2; RUN: -check-prefix=ALL -check-prefix=GP32 \ 3; RUN: -check-prefix=M2 4; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ 5; RUN: -check-prefix=ALL -check-prefix=GP32 \ 6; RUN: -check-prefix=32R1-R5 7; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ 8; RUN: -check-prefix=ALL -check-prefix=GP32 \ 9; RUN: -check-prefix=32R1-R5 10; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ 11; RUN: -check-prefix=ALL -check-prefix=GP32 \ 12; RUN: -check-prefix=32R1-R5 13; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ 14; RUN: -check-prefix=ALL -check-prefix=GP32 \ 15; RUN: -check-prefix=32R1-R5 16; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ 17; RUN: -check-prefix=ALL -check-prefix=GP32 \ 18; RUN: -check-prefix=32R6 19; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ 20; RUN: -check-prefix=ALL -check-prefix=GP64 \ 21; RUN: -check-prefix=M3 22; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ 23; RUN: -check-prefix=ALL -check-prefix=GP64 \ 24; RUN: -check-prefix=GP64-NOT-R6 25; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ 26; RUN: -check-prefix=ALL -check-prefix=GP64 \ 27; RUN: -check-prefix=GP64-NOT-R6 28; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ 29; RUN: -check-prefix=ALL -check-prefix=GP64 \ 30; RUN: -check-prefix=GP64-NOT-R6 31; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ 32; RUN: -check-prefix=ALL -check-prefix=GP64 \ 33; RUN: -check-prefix=GP64-NOT-R6 34; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ 35; RUN: -check-prefix=ALL -check-prefix=GP64 \ 36; RUN: -check-prefix=GP64-NOT-R6 37; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ 38; RUN: -check-prefix=ALL -check-prefix=GP64 \ 39; RUN: -check-prefix=64R6 40 41define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) { 42entry: 43; ALL-LABEL: lshr_i1: 44 45 ; ALL: move $2, $4 46 47 %r = lshr i1 %a, %b 48 ret i1 %r 49} 50 51define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) { 52entry: 53; ALL-LABEL: lshr_i8: 54 55 ; ALL: srlv $[[T0:[0-9]+]], $4, $5 56 ; ALL: andi $2, $[[T0]], 255 57 58 %r = lshr i8 %a, %b 59 ret i8 %r 60} 61 62define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) { 63entry: 64; ALL-LABEL: lshr_i16: 65 66 ; ALL: srlv $[[T0:[0-9]+]], $4, $5 67 ; ALL: andi $2, $[[T0]], 65535 68 69 %r = lshr i16 %a, %b 70 ret i16 %r 71} 72 73define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) { 74entry: 75; ALL-LABEL: lshr_i32: 76 77 ; ALL: srlv $2, $4, $5 78 79 %r = lshr i32 %a, %b 80 ret i32 %r 81} 82 83define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { 84entry: 85; ALL-LABEL: lshr_i64: 86 87 ; M2: srlv $[[T0:[0-9]+]], $4, $7 88 ; M2: andi $[[T1:[0-9]+]], $7, 32 89 ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] 90 ; M2: move $3, $[[T0]] 91 ; M2: srlv $[[T2:[0-9]+]], $5, $7 92 ; M2: not $[[T3:[0-9]+]], $7 93 ; M2: sll $[[T4:[0-9]+]], $4, 1 94 ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] 95 ; M2: or $3, $[[T3]], $[[T2]] 96 ; M2: $[[BB0]]: 97 ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] 98 ; M2: addiu $2, $zero, 0 99 ; M2: move $2, $[[T0]] 100 ; M2: $[[BB1]]: 101 ; M2: jr $ra 102 ; M2: nop 103 104 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7 105 ; 32R1-R5: not $[[T1:[0-9]+]], $7 106 ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1 107 ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] 108 ; 32R1-R5: or $3, $[[T3]], $[[T0]] 109 ; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7 110 ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 111 ; 32R1-R5: movn $3, $[[T4]], $[[T5]] 112 ; 32R1-R5: jr $ra 113 ; 32R1-R5: movn $2, $zero, $[[T5]] 114 115 ; 32R6: srlv $[[T0:[0-9]+]], $5, $7 116 ; 32R6: not $[[T1:[0-9]+]], $7 117 ; 32R6: sll $[[T2:[0-9]+]], $4, 1 118 ; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] 119 ; 32R6: or $[[T4:[0-9]+]], $[[T3]], $[[T0]] 120 ; 32R6: andi $[[T5:[0-9]+]], $7, 32 121 ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]] 122 ; 32R6: srlv $[[T7:[0-9]+]], $4, $7 123 ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] 124 ; 32R6: or $3, $[[T8]], $[[T6]] 125 ; 32R6: jr $ra 126 ; 32R6: seleqz $2, $[[T7]], $[[T5]] 127 128 ; GP64: dsrlv $2, $4, $5 129 130 %r = lshr i64 %a, %b 131 ret i64 %r 132} 133 134define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { 135entry: 136; ALL-LABEL: lshr_i128: 137 138 ; GP32: lw $25, %call16(__lshrti3)($gp) 139 140 ; M3: sll $[[T0:[0-9]+]], $7, 0 141 ; M3: dsrlv $[[T1:[0-9]+]], $4, $7 142 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 143 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] 144 ; M3: move $3, $[[T1]] 145 ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 146 ; M3: dsll $[[T5:[0-9]+]], $4, 1 147 ; M3: not $[[T6:[0-9]+]], $[[T0]] 148 ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] 149 ; M3: or $3, $[[T7]], $[[T4]] 150 ; M3: $[[BB0]]: 151 ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] 152 ; M3: daddiu $2, $zero, 0 153 ; M3: move $2, $[[T1]] 154 ; M3: $[[BB1]]: 155 ; M3: jr $ra 156 ; M3: nop 157 158 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 159 ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 160 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 161 ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] 162 ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] 163 ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]] 164 ; GP64-NOT-R6: dsrlv $2, $4, $7 165 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64 166 ; GP64-NOT-R6: movn $3, $2, $[[T5]] 167 ; GP64-NOT-R6: jr $ra 168 ; GP64-NOT-R6: movn $2, $zero, $1 169 170 ; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7 171 ; 64R6: dsll $[[T1:[0-9]+]], $4, 1 172 ; 64R6: sll $[[T2:[0-9]+]], $7, 0 173 ; 64R6: not $[[T3:[0-9]+]], $[[T2]] 174 ; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] 175 ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]] 176 ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64 177 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 178 ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] 179 ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7 180 ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] 181 ; 64R6: or $3, $[[T10]], $[[T8]] 182 ; 64R6: jr $ra 183 ; 64R6: seleqz $2, $[[T9]], $[[T7]] 184 185 %r = lshr i128 %a, %b 186 ret i128 %r 187} 188