1; Check that [sl]dc1 are normally emitted. MIPS32r2 should have [sl]dxc1 too. 2; RUN: llc -march=mipsel -mcpu=mips32 < %s | \ 3; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1-LDC1 4; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | \ 5; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2-LDXC1 6; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | \ 7; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6-LDC1 8 9; Check that -mno-ldc1-sdc1 disables [sl]dc1 10; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ 11; RUN: -mcpu=mips32 < %s | \ 12; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \ 13; RUN: -check-prefix=32R1-LE -check-prefix=32R1-LE-PIC 14; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ 15; RUN: -mcpu=mips32r2 < %s | \ 16; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \ 17; RUN: -check-prefix=32R2-LE -check-prefix=32R2-LE-PIC 18; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ 19; RUN: -mcpu=mips32r6 < %s | \ 20; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \ 21; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-PIC 22 23; Check again for big-endian 24; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ 25; RUN: -mcpu=mips32 < %s | \ 26; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \ 27; RUN: -check-prefix=32R1-BE -check-prefix=32R1-BE-PIC 28; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ 29; RUN: -mcpu=mips32r2 < %s | \ 30; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \ 31; RUN: -check-prefix=32R2-BE -check-prefix=32R2-BE-PIC 32; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ 33; RUN: -mcpu=mips32r6 < %s | \ 34; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \ 35; RUN: -check-prefix=32R6-BE -check-prefix=32R6-BE-PIC 36 37; Check again for the static relocation model 38; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ 39; RUN: -mcpu=mips32 < %s | \ 40; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \ 41; RUN: -check-prefix=32R1-LE -check-prefix=32R1-LE-STATIC 42; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ 43; RUN: -mcpu=mips32r2 < %s | \ 44; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \ 45; RUN: -check-prefix=32R2-LE -check-prefix=32R2-LE-STATIC 46; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ 47; RUN: -mcpu=mips32r6 < %s | \ 48; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \ 49; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-STATIC 50 51@g0 = common global double 0.000000e+00, align 8 52 53; ALL-LABEL: test_ldc1: 54 55; 32R1-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 56; 32R1-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 57; 32R1-LE-PIC-DAG: mtc1 $[[R0]], $f0 58; 32R1-LE-PIC-DAG: mtc1 $[[R1]], $f1 59 60; 32R2-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 61; 32R2-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 62; 32R2-LE-PIC-DAG: mtc1 $[[R0]], $f0 63; 32R2-LE-PIC-DAG: mthc1 $[[R1]], $f0 64 65; 32R6-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 66; 32R6-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 67; 32R6-LE-PIC-DAG: mtc1 $[[R0]], $f0 68; 32R6-LE-PIC-DAG: mthc1 $[[R1]], $f0 69 70; 32R1-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0) 71; 32R1-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]]) 72; 32R1-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0) 73; 32R1-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]]) 74; 32R1-LE-STATIC-DAG: mtc1 $[[R1]], $f0 75; 32R1-LE-STATIC-DAG: mtc1 $[[R3]], $f1 76 77; 32R2-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0) 78; 32R2-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]]) 79; 32R2-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0) 80; 32R2-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]]) 81; 32R2-LE-STATIC-DAG: mtc1 $[[R1]], $f0 82; 32R2-LE-STATIC-DAG: mthc1 $[[R3]], $f0 83 84; 32R6-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0) 85; 32R6-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]]) 86; 32R6-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0) 87; 32R6-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]]) 88; 32R6-LE-STATIC-DAG: mtc1 $[[R1]], $f0 89; 32R6-LE-STATIC-DAG: mthc1 $[[R3]], $f0 90 91; 32R1-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 92; 32R1-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 93; 32R1-BE-PIC-DAG: mtc1 $[[R1]], $f0 94; 32R1-BE-PIC-DAG: mtc1 $[[R0]], $f1 95 96; 32R2-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 97; 32R2-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 98; 32R2-BE-PIC-DAG: mtc1 $[[R1]], $f0 99; 32R2-BE-PIC-DAG: mthc1 $[[R0]], $f0 100 101; 32R6-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 102; 32R6-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 103; 32R6-BE-PIC-DAG: mtc1 $[[R1]], $f0 104; 32R6-BE-PIC-DAG: mthc1 $[[R0]], $f0 105 106; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}}) 107 108; 32R2-LDXC1: ldc1 $f0, 0(${{[0-9]+}}) 109 110; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}}) 111 112define double @test_ldc1() { 113entry: 114 %0 = load double, double* @g0, align 8 115 ret double %0 116} 117 118; ALL-LABEL: test_sdc1: 119 120; 32R1-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 121; 32R1-LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13 122; 32R1-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}}) 123; 32R1-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}}) 124 125; 32R2-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 126; 32R2-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 127; 32R2-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}}) 128; 32R2-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}}) 129 130; 32R6-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 131; 32R6-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 132; 32R6-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}}) 133; 32R6-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}}) 134 135; 32R1-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 136; 32R1-LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13 137; 32R1-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0) 138; 32R1-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]]) 139; 32R1-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0) 140; 32R1-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]]) 141 142; 32R2-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 143; 32R2-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 144; 32R2-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0) 145; 32R2-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]]) 146; 32R2-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0) 147; 32R2-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]]) 148 149; 32R6-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 150; 32R6-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 151; 32R6-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0) 152; 32R6-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]]) 153; 32R6-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0) 154; 32R6-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]]) 155 156; 32R1-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 157; 32R1-BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13 158; 32R1-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}}) 159; 32R1-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}}) 160 161; 32R2-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 162; 32R2-BE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 163; 32R2-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}}) 164; 32R2-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}}) 165 166; 32R6-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 167; 32R6-BE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 168; 32R6-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}}) 169; 32R6-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}}) 170 171; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) 172 173; 32R2-LDXC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) 174 175; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) 176 177define void @test_sdc1(double %a) { 178entry: 179 store double %a, double* @g0, align 8 180 ret void 181} 182 183; ALL-LABEL: test_ldxc1: 184 185; 32R1-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 186; 32R1-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 187; 32R1-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}}) 188; 32R1-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}}) 189; 32R1-DAG: mtc1 $[[R0]], $f0 190; 32R1-DAG: mtc1 $[[R1]], $f1 191 192; 32R2-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 193; 32R2-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 194; 32R2-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}}) 195; 32R2-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}}) 196; 32R2-DAG: mtc1 $[[R0]], $f0 197; 32R2-DAG: mthc1 $[[R1]], $f0 198 199; 32R6-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 200; 32R6-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 201; 32R6-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}}) 202; 32R6-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}}) 203; 32R6-DAG: mtc1 $[[R0]], $f0 204; 32R6-DAG: mthc1 $[[R1]], $f0 205 206; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}}) 207 208; 32R2-LDXC1: sll $[[OFFSET:[0-9]+]], $5, 3 209; 32R2-LDXC1: ldxc1 $f0, $[[OFFSET]]($4) 210 211; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}}) 212 213define double @test_ldxc1(double* nocapture readonly %a, i32 %i) { 214entry: 215 %arrayidx = getelementptr inbounds double, double* %a, i32 %i 216 %0 = load double, double* %arrayidx, align 8 217 ret double %0 218} 219 220; ALL-LABEL: test_sdxc1: 221 222; 32R1-DAG: mfc1 $[[R0:[0-9]+]], $f12 223; 32R1-DAG: mfc1 $[[R1:[0-9]+]], $f13 224; 32R1-DAG: sw $[[R0]], 0(${{[0-9]+}}) 225; 32R1-DAG: sw $[[R1]], 4(${{[0-9]+}}) 226 227; 32R2-DAG: mfc1 $[[R0:[0-9]+]], $f12 228; 32R2-DAG: mfhc1 $[[R1:[0-9]+]], $f12 229; 32R2-DAG: sw $[[R0]], 0(${{[0-9]+}}) 230; 32R2-DAG: sw $[[R1]], 4(${{[0-9]+}}) 231 232; 32R6-DAG: mfc1 $[[R0:[0-9]+]], $f12 233; 32R6-DAG: mfhc1 $[[R1:[0-9]+]], $f12 234; 32R6-DAG: sw $[[R0]], 0(${{[0-9]+}}) 235; 32R6-DAG: sw $[[R1]], 4(${{[0-9]+}}) 236 237; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) 238 239; 32R2-LDXC1: sll $[[OFFSET:[0-9]+]], $7, 3 240; 32R2-LDXC1: sdxc1 $f{{[0-9]+}}, $[[OFFSET]]($6) 241 242; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) 243 244define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) { 245entry: 246 %arrayidx = getelementptr inbounds double, double* %a, i32 %i 247 store double %b, double* %arrayidx, align 8 248 ret void 249} 250