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1# RUN: llc -o - %s -start-after=if-converter | FileCheck %s
2
3--- |
4  target datalayout = "E-m:e-i64:64-n32:64"
5  target triple = "powerpc64-unknown-linux-gnu"
6
7  %struct.rwlock_t.0.22.58.68.242.244 = type {}
8
9  @tasklist_lock = external global %struct.rwlock_t.0.22.58.68.242.244, align 1
10
11  ; Function Attrs: nounwind
12  define void @mm_update_next_owner(i8** %p1, i32* %p2) #0 {
13  entry:
14    %0 = load i8*, i8** %p1, align 8
15    br i1 undef, label %do.body.92, label %for.body.21
16
17  for.body.21:                                      ; preds = %entry
18    unreachable
19
20  do.body.92:                                       ; preds = %entry
21    %usage = getelementptr inbounds i8, i8* %0, i64 -48
22    %counter.i = bitcast i8* %usage to i32*
23    %call95 = tail call signext i32 bitcast (i32 (...)* @__raw_read_unlock to i32 (%struct.rwlock_t.0.22.58.68.242.244*)*)(%struct.rwlock_t.0.22.58.68.242.244* nonnull @tasklist_lock) #1
24    store volatile i32 0, i32* %p2, align 4
25    tail call void asm sideeffect "#compiler barrier", "~{memory}"() #1
26    %1 = tail call i32 asm sideeffect "\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", "=&r,r,~{cc},~{xer},~{memory}"(i32* %counter.i) #1
27    %cmp.i = icmp eq i32 %1, 0
28    br i1 %cmp.i, label %if.then.i, label %put_task_struct.exit
29
30  if.then.i:                                        ; preds = %do.body.92
31    unreachable
32
33  put_task_struct.exit:                             ; preds = %do.body.92
34    ret void
35  }
36
37  declare signext i32 @__raw_read_unlock(...)
38
39  attributes #0 = { nounwind "target-cpu"="pwr7" }
40  attributes #1 = { nounwind }
41
42...
43---
44name:            mm_update_next_owner
45alignment:       4
46exposesReturnsTwice: false
47hasInlineAsm:    true
48isSSA:           false
49tracksRegLiveness: true
50tracksSubRegLiveness: false
51liveins:
52  - { reg: '%x3' }
53  - { reg: '%x4' }
54calleeSavedRegisters: [ '%cr2', '%cr3', '%cr4', '%f14', '%f15', '%f16',
55                        '%f17', '%f18', '%f19', '%f20', '%f21', '%f22',
56                        '%f23', '%f24', '%f25', '%f26', '%f27', '%f28',
57                        '%f29', '%f30', '%f31', '%r14', '%r15', '%r16',
58                        '%r17', '%r18', '%r19', '%r20', '%r21', '%r22',
59                        '%r23', '%r24', '%r25', '%r26', '%r27', '%r28',
60                        '%r29', '%r30', '%r31', '%v20', '%v21', '%v22',
61                        '%v23', '%v24', '%v25', '%v26', '%v27', '%v28',
62                        '%v29', '%v30', '%v31', '%vf20', '%vf21', '%vf22',
63                        '%vf23', '%vf24', '%vf25', '%vf26', '%vf27', '%vf28',
64                        '%vf29', '%vf30', '%vf31', '%x14', '%x15', '%x16',
65                        '%x17', '%x18', '%x19', '%x20', '%x21', '%x22',
66                        '%x23', '%x24', '%x25', '%x26', '%x27', '%x28',
67                        '%x29', '%x30', '%x31', '%cr2eq', '%cr3eq', '%cr4eq',
68                        '%cr2gt', '%cr3gt', '%cr4gt', '%cr2lt', '%cr3lt',
69                        '%cr4lt', '%cr2un', '%cr3un', '%cr4un' ]
70frameInfo:
71  isFrameAddressTaken: false
72  isReturnAddressTaken: false
73  hasStackMap:     false
74  hasPatchPoint:   false
75  stackSize:       144
76  offsetAdjustment: 0
77  maxAlignment:    0
78  adjustsStack:    true
79  hasCalls:        true
80  maxCallFrameSize: 112
81  hasOpaqueSPAdjustment: false
82  hasVAStart:      false
83  hasMustTailInVarArgFunc: false
84fixedStack:
85  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
86  - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%x29' }
87body:             |
88  bb.0.entry:
89    liveins: %x3, %x4, %x29, %x30, %x29, %x30
90
91    %x0 = MFLR8 implicit %lr8
92    STD %x0, 16, %x1
93    %x1 = STDU %x1, -144, %x1
94    STD killed %x29, 120, %x1 :: (store 8 into %fixed-stack.1)
95    STD killed %x30, 128, %x1 :: (store 8 into %fixed-stack.0, align 16)
96    %x30 = OR8 %x4, %x4
97    %x3 = LD 0, killed %x3 :: (load 8 from %ir.p1)
98    %x29 = ADDI8 killed %x3, -48
99    %x3 = ADDIStocHA %x2, @tasklist_lock
100    %x3 = LDtocL @tasklist_lock, killed %x3, implicit %x2 :: (load 8 from got)
101    BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def %lr8, implicit %rm, implicit %x3, implicit %x2, implicit-def %r1, implicit-def dead %x3
102    %r3 = LI 0
103    STW killed %r3, 0, killed %x30 :: (volatile store 4 into %ir.p2)
104    INLINEASM $"#compiler barrier", 25
105    INLINEASM $"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber %r3, 851977, killed %x29, 12, implicit-def dead early-clobber %cr0
106    ; CHECK-LABEL: @mm_update_next_owner
107    ; CHECK-NOT: lwarx 29, 0, 29
108    ; CHECK-NOT: stwcx. 29, 0, 29
109    %cr0 = CMPLWI killed %r3, 0
110    %x30 = LD 128, %x1 :: (load 8 from %fixed-stack.0, align 16)
111    %x29 = LD 120, %x1 :: (load 8 from %fixed-stack.1)
112    %x1 = ADDI8 %x1, 144
113    %x0 = LD 16, %x1
114    MTLR8 %x0, implicit-def %lr8
115    BLR8 implicit %lr8, implicit %rm
116
117...
118