1; RUN: llc < %s | FileCheck %s 2target datalayout = "E-m:e-i64:64-n32:64" 3target triple = "powerpc64-unknown-linux-gnu" 4 5; FIXME: We should check the operands to the cr* logical operation itself, but 6; unfortunately, FileCheck does not yet understand how to do arithmetic, so we 7; can't do so without introducing a register-allocation dependency. 8 9define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 10entry: 11 %cmp1 = icmp eq i32 %c3, %c4 12 %cmp3tmp = icmp eq i32 %c1, %c2 13 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 14 %cond = select i1 %cmp3, i32 %a1, i32 %a2 15 ret i32 %cond 16 17; CHECK-LABEL: @testi32slt 18; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 19; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 20; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 21; CHECK: isel 3, 7, 8, [[REG1]] 22; CHECK: blr 23} 24 25define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 26entry: 27 %cmp1 = icmp eq i32 %c3, %c4 28 %cmp3tmp = icmp eq i32 %c1, %c2 29 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 30 %cond = select i1 %cmp3, i32 %a1, i32 %a2 31 ret i32 %cond 32 33; CHECK-LABEL: @testi32ult 34; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 35; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 36; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 37; CHECK: isel 3, 7, 8, [[REG1]] 38; CHECK: blr 39} 40 41define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 42entry: 43 %cmp1 = icmp eq i32 %c3, %c4 44 %cmp3tmp = icmp eq i32 %c1, %c2 45 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 46 %cond = select i1 %cmp3, i32 %a1, i32 %a2 47 ret i32 %cond 48 49; CHECK-LABEL: @testi32sle 50; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 51; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 52; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 53; CHECK: isel 3, 7, 8, [[REG1]] 54; CHECK: blr 55} 56 57define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 58entry: 59 %cmp1 = icmp eq i32 %c3, %c4 60 %cmp3tmp = icmp eq i32 %c1, %c2 61 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 62 %cond = select i1 %cmp3, i32 %a1, i32 %a2 63 ret i32 %cond 64 65; CHECK-LABEL: @testi32ule 66; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 67; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 68; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 69; CHECK: isel 3, 7, 8, [[REG1]] 70; CHECK: blr 71} 72 73define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 74entry: 75 %cmp1 = icmp eq i32 %c3, %c4 76 %cmp3tmp = icmp eq i32 %c1, %c2 77 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 78 %cond = select i1 %cmp3, i32 %a1, i32 %a2 79 ret i32 %cond 80 81; CHECK-LABEL: @testi32eq 82; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 83; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 84; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 85; CHECK: isel 3, 7, 8, [[REG1]] 86; CHECK: blr 87} 88 89define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 90entry: 91 %cmp1 = icmp eq i32 %c3, %c4 92 %cmp3tmp = icmp eq i32 %c1, %c2 93 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 94 %cond = select i1 %cmp3, i32 %a1, i32 %a2 95 ret i32 %cond 96 97; CHECK-LABEL: @testi32sge 98; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 99; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 100; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 101; CHECK: isel 3, 7, 8, [[REG1]] 102; CHECK: blr 103} 104 105define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 106entry: 107 %cmp1 = icmp eq i32 %c3, %c4 108 %cmp3tmp = icmp eq i32 %c1, %c2 109 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 110 %cond = select i1 %cmp3, i32 %a1, i32 %a2 111 ret i32 %cond 112 113; CHECK-LABEL: @testi32uge 114; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 115; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 116; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 117; CHECK: isel 3, 7, 8, [[REG1]] 118; CHECK: blr 119} 120 121define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 122entry: 123 %cmp1 = icmp eq i32 %c3, %c4 124 %cmp3tmp = icmp eq i32 %c1, %c2 125 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 126 %cond = select i1 %cmp3, i32 %a1, i32 %a2 127 ret i32 %cond 128 129; CHECK-LABEL: @testi32sgt 130; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 131; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 132; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 133; CHECK: isel 3, 7, 8, [[REG1]] 134; CHECK: blr 135} 136 137define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 138entry: 139 %cmp1 = icmp eq i32 %c3, %c4 140 %cmp3tmp = icmp eq i32 %c1, %c2 141 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 142 %cond = select i1 %cmp3, i32 %a1, i32 %a2 143 ret i32 %cond 144 145; CHECK-LABEL: @testi32ugt 146; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 147; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 148; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 149; CHECK: isel 3, 7, 8, [[REG1]] 150; CHECK: blr 151} 152 153define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 154entry: 155 %cmp1 = icmp eq i32 %c3, %c4 156 %cmp3tmp = icmp eq i32 %c1, %c2 157 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 158 %cond = select i1 %cmp3, i32 %a1, i32 %a2 159 ret i32 %cond 160 161; CHECK-LABEL: @testi32ne 162; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 163; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 164; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 165; CHECK: isel 3, 7, 8, [[REG1]] 166; CHECK: blr 167} 168 169define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 170entry: 171 %cmp1 = icmp eq i64 %c3, %c4 172 %cmp3tmp = icmp eq i64 %c1, %c2 173 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 174 %cond = select i1 %cmp3, i64 %a1, i64 %a2 175 ret i64 %cond 176 177; CHECK-LABEL: @testi64slt 178; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 179; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 180; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 181; CHECK: isel 3, 7, 8, [[REG1]] 182; CHECK: blr 183} 184 185define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 186entry: 187 %cmp1 = icmp eq i64 %c3, %c4 188 %cmp3tmp = icmp eq i64 %c1, %c2 189 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 190 %cond = select i1 %cmp3, i64 %a1, i64 %a2 191 ret i64 %cond 192 193; CHECK-LABEL: @testi64ult 194; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 195; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 196; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 197; CHECK: isel 3, 7, 8, [[REG1]] 198; CHECK: blr 199} 200 201define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 202entry: 203 %cmp1 = icmp eq i64 %c3, %c4 204 %cmp3tmp = icmp eq i64 %c1, %c2 205 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 206 %cond = select i1 %cmp3, i64 %a1, i64 %a2 207 ret i64 %cond 208 209; CHECK-LABEL: @testi64sle 210; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 211; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 212; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 213; CHECK: isel 3, 7, 8, [[REG1]] 214; CHECK: blr 215} 216 217define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 218entry: 219 %cmp1 = icmp eq i64 %c3, %c4 220 %cmp3tmp = icmp eq i64 %c1, %c2 221 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 222 %cond = select i1 %cmp3, i64 %a1, i64 %a2 223 ret i64 %cond 224 225; CHECK-LABEL: @testi64ule 226; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 227; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 228; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 229; CHECK: isel 3, 7, 8, [[REG1]] 230; CHECK: blr 231} 232 233define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 234entry: 235 %cmp1 = icmp eq i64 %c3, %c4 236 %cmp3tmp = icmp eq i64 %c1, %c2 237 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 238 %cond = select i1 %cmp3, i64 %a1, i64 %a2 239 ret i64 %cond 240 241; CHECK-LABEL: @testi64eq 242; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 243; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 244; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 245; CHECK: isel 3, 7, 8, [[REG1]] 246; CHECK: blr 247} 248 249define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 250entry: 251 %cmp1 = icmp eq i64 %c3, %c4 252 %cmp3tmp = icmp eq i64 %c1, %c2 253 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 254 %cond = select i1 %cmp3, i64 %a1, i64 %a2 255 ret i64 %cond 256 257; CHECK-LABEL: @testi64sge 258; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 259; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 260; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 261; CHECK: isel 3, 7, 8, [[REG1]] 262; CHECK: blr 263} 264 265define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 266entry: 267 %cmp1 = icmp eq i64 %c3, %c4 268 %cmp3tmp = icmp eq i64 %c1, %c2 269 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 270 %cond = select i1 %cmp3, i64 %a1, i64 %a2 271 ret i64 %cond 272 273; CHECK-LABEL: @testi64uge 274; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 275; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 276; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 277; CHECK: isel 3, 7, 8, [[REG1]] 278; CHECK: blr 279} 280 281define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 282entry: 283 %cmp1 = icmp eq i64 %c3, %c4 284 %cmp3tmp = icmp eq i64 %c1, %c2 285 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 286 %cond = select i1 %cmp3, i64 %a1, i64 %a2 287 ret i64 %cond 288 289; CHECK-LABEL: @testi64sgt 290; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 291; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 292; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 293; CHECK: isel 3, 7, 8, [[REG1]] 294; CHECK: blr 295} 296 297define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 298entry: 299 %cmp1 = icmp eq i64 %c3, %c4 300 %cmp3tmp = icmp eq i64 %c1, %c2 301 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 302 %cond = select i1 %cmp3, i64 %a1, i64 %a2 303 ret i64 %cond 304 305; CHECK-LABEL: @testi64ugt 306; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 307; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 308; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 309; CHECK: isel 3, 7, 8, [[REG1]] 310; CHECK: blr 311} 312 313define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 314entry: 315 %cmp1 = icmp eq i64 %c3, %c4 316 %cmp3tmp = icmp eq i64 %c1, %c2 317 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 318 %cond = select i1 %cmp3, i64 %a1, i64 %a2 319 ret i64 %cond 320 321; CHECK-LABEL: @testi64ne 322; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 323; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 324; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 325; CHECK: isel 3, 7, 8, [[REG1]] 326; CHECK: blr 327} 328 329define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 330entry: 331 %cmp1 = fcmp oeq float %c3, %c4 332 %cmp3tmp = fcmp oeq float %c1, %c2 333 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 334 %cond = select i1 %cmp3, float %a1, float %a2 335 ret float %cond 336 337; CHECK-LABEL: @testfloatslt 338; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 339; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 340; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 341; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 342; CHECK: fmr 5, 6 343; CHECK: .LBB[[BB]]: 344; CHECK: fmr 1, 5 345; CHECK: blr 346} 347 348define float @testfloatult(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 349entry: 350 %cmp1 = fcmp oeq float %c3, %c4 351 %cmp3tmp = fcmp oeq float %c1, %c2 352 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 353 %cond = select i1 %cmp3, float %a1, float %a2 354 ret float %cond 355 356; CHECK-LABEL: @testfloatult 357; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 358; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 359; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 360; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 361; CHECK: fmr 5, 6 362; CHECK: .LBB[[BB]]: 363; CHECK: fmr 1, 5 364; CHECK: blr 365} 366 367define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 368entry: 369 %cmp1 = fcmp oeq float %c3, %c4 370 %cmp3tmp = fcmp oeq float %c1, %c2 371 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 372 %cond = select i1 %cmp3, float %a1, float %a2 373 ret float %cond 374 375; CHECK-LABEL: @testfloatsle 376; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 377; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 378; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 379; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 380; CHECK: fmr 5, 6 381; CHECK: .LBB[[BB]]: 382; CHECK: fmr 1, 5 383; CHECK: blr 384} 385 386define float @testfloatule(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 387entry: 388 %cmp1 = fcmp oeq float %c3, %c4 389 %cmp3tmp = fcmp oeq float %c1, %c2 390 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 391 %cond = select i1 %cmp3, float %a1, float %a2 392 ret float %cond 393 394; CHECK-LABEL: @testfloatule 395; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 396; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 397; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 398; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 399; CHECK: fmr 5, 6 400; CHECK: .LBB[[BB]]: 401; CHECK: fmr 1, 5 402; CHECK: blr 403} 404 405define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 406entry: 407 %cmp1 = fcmp oeq float %c3, %c4 408 %cmp3tmp = fcmp oeq float %c1, %c2 409 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 410 %cond = select i1 %cmp3, float %a1, float %a2 411 ret float %cond 412 413; CHECK-LABEL: @testfloateq 414; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 415; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 416; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 417; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 418; CHECK: fmr 5, 6 419; CHECK: .LBB[[BB]]: 420; CHECK: fmr 1, 5 421; CHECK: blr 422} 423 424define float @testfloatsge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 425entry: 426 %cmp1 = fcmp oeq float %c3, %c4 427 %cmp3tmp = fcmp oeq float %c1, %c2 428 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 429 %cond = select i1 %cmp3, float %a1, float %a2 430 ret float %cond 431 432; CHECK-LABEL: @testfloatsge 433; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 434; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 435; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 436; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 437; CHECK: fmr 5, 6 438; CHECK: .LBB[[BB]]: 439; CHECK: fmr 1, 5 440; CHECK: blr 441} 442 443define float @testfloatuge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 444entry: 445 %cmp1 = fcmp oeq float %c3, %c4 446 %cmp3tmp = fcmp oeq float %c1, %c2 447 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 448 %cond = select i1 %cmp3, float %a1, float %a2 449 ret float %cond 450 451; CHECK-LABEL: @testfloatuge 452; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 453; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 454; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 455; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 456; CHECK: fmr 5, 6 457; CHECK: .LBB[[BB]]: 458; CHECK: fmr 1, 5 459; CHECK: blr 460} 461 462define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 463entry: 464 %cmp1 = fcmp oeq float %c3, %c4 465 %cmp3tmp = fcmp oeq float %c1, %c2 466 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 467 %cond = select i1 %cmp3, float %a1, float %a2 468 ret float %cond 469 470; CHECK-LABEL: @testfloatsgt 471; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 472; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 473; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 474; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 475; CHECK: fmr 5, 6 476; CHECK: .LBB[[BB]]: 477; CHECK: fmr 1, 5 478; CHECK: blr 479} 480 481define float @testfloatugt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 482entry: 483 %cmp1 = fcmp oeq float %c3, %c4 484 %cmp3tmp = fcmp oeq float %c1, %c2 485 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 486 %cond = select i1 %cmp3, float %a1, float %a2 487 ret float %cond 488 489; CHECK-LABEL: @testfloatugt 490; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 491; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 492; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 493; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 494; CHECK: fmr 5, 6 495; CHECK: .LBB[[BB]]: 496; CHECK: fmr 1, 5 497; CHECK: blr 498} 499 500define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 501entry: 502 %cmp1 = fcmp oeq float %c3, %c4 503 %cmp3tmp = fcmp oeq float %c1, %c2 504 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 505 %cond = select i1 %cmp3, float %a1, float %a2 506 ret float %cond 507 508; CHECK-LABEL: @testfloatne 509; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 510; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 511; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 512; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 513; CHECK: fmr 5, 6 514; CHECK: .LBB[[BB]]: 515; CHECK: fmr 1, 5 516; CHECK: blr 517} 518 519define double @testdoubleslt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 520entry: 521 %cmp1 = fcmp oeq double %c3, %c4 522 %cmp3tmp = fcmp oeq double %c1, %c2 523 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 524 %cond = select i1 %cmp3, double %a1, double %a2 525 ret double %cond 526 527; CHECK-LABEL: @testdoubleslt 528; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 529; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 530; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 531; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 532; CHECK: fmr 5, 6 533; CHECK: .LBB[[BB]]: 534; CHECK: fmr 1, 5 535; CHECK: blr 536} 537 538define double @testdoubleult(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 539entry: 540 %cmp1 = fcmp oeq double %c3, %c4 541 %cmp3tmp = fcmp oeq double %c1, %c2 542 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 543 %cond = select i1 %cmp3, double %a1, double %a2 544 ret double %cond 545 546; CHECK-LABEL: @testdoubleult 547; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 548; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 549; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 550; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 551; CHECK: fmr 5, 6 552; CHECK: .LBB[[BB]]: 553; CHECK: fmr 1, 5 554; CHECK: blr 555} 556 557define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 558entry: 559 %cmp1 = fcmp oeq double %c3, %c4 560 %cmp3tmp = fcmp oeq double %c1, %c2 561 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 562 %cond = select i1 %cmp3, double %a1, double %a2 563 ret double %cond 564 565; CHECK-LABEL: @testdoublesle 566; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 567; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 568; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 569; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 570; CHECK: fmr 5, 6 571; CHECK: .LBB[[BB]]: 572; CHECK: fmr 1, 5 573; CHECK: blr 574} 575 576define double @testdoubleule(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 577entry: 578 %cmp1 = fcmp oeq double %c3, %c4 579 %cmp3tmp = fcmp oeq double %c1, %c2 580 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 581 %cond = select i1 %cmp3, double %a1, double %a2 582 ret double %cond 583 584; CHECK-LABEL: @testdoubleule 585; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 586; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 587; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 588; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 589; CHECK: fmr 5, 6 590; CHECK: .LBB[[BB]]: 591; CHECK: fmr 1, 5 592; CHECK: blr 593} 594 595define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 596entry: 597 %cmp1 = fcmp oeq double %c3, %c4 598 %cmp3tmp = fcmp oeq double %c1, %c2 599 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 600 %cond = select i1 %cmp3, double %a1, double %a2 601 ret double %cond 602 603; CHECK-LABEL: @testdoubleeq 604; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 605; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 606; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 607; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 608; CHECK: fmr 5, 6 609; CHECK: .LBB[[BB]]: 610; CHECK: fmr 1, 5 611; CHECK: blr 612} 613 614define double @testdoublesge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 615entry: 616 %cmp1 = fcmp oeq double %c3, %c4 617 %cmp3tmp = fcmp oeq double %c1, %c2 618 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 619 %cond = select i1 %cmp3, double %a1, double %a2 620 ret double %cond 621 622; CHECK-LABEL: @testdoublesge 623; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 624; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 625; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 626; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 627; CHECK: fmr 5, 6 628; CHECK: .LBB[[BB]]: 629; CHECK: fmr 1, 5 630; CHECK: blr 631} 632 633define double @testdoubleuge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 634entry: 635 %cmp1 = fcmp oeq double %c3, %c4 636 %cmp3tmp = fcmp oeq double %c1, %c2 637 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 638 %cond = select i1 %cmp3, double %a1, double %a2 639 ret double %cond 640 641; CHECK-LABEL: @testdoubleuge 642; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 643; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 644; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 645; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 646; CHECK: fmr 5, 6 647; CHECK: .LBB[[BB]]: 648; CHECK: fmr 1, 5 649; CHECK: blr 650} 651 652define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 653entry: 654 %cmp1 = fcmp oeq double %c3, %c4 655 %cmp3tmp = fcmp oeq double %c1, %c2 656 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 657 %cond = select i1 %cmp3, double %a1, double %a2 658 ret double %cond 659 660; CHECK-LABEL: @testdoublesgt 661; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 662; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 663; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 664; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 665; CHECK: fmr 5, 6 666; CHECK: .LBB[[BB]]: 667; CHECK: fmr 1, 5 668; CHECK: blr 669} 670 671define double @testdoubleugt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 672entry: 673 %cmp1 = fcmp oeq double %c3, %c4 674 %cmp3tmp = fcmp oeq double %c1, %c2 675 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 676 %cond = select i1 %cmp3, double %a1, double %a2 677 ret double %cond 678 679; CHECK-LABEL: @testdoubleugt 680; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 681; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 682; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 683; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 684; CHECK: fmr 5, 6 685; CHECK: .LBB[[BB]]: 686; CHECK: fmr 1, 5 687; CHECK: blr 688} 689 690define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 691entry: 692 %cmp1 = fcmp oeq double %c3, %c4 693 %cmp3tmp = fcmp oeq double %c1, %c2 694 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 695 %cond = select i1 %cmp3, double %a1, double %a2 696 ret double %cond 697 698; CHECK-LABEL: @testdoublene 699; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 700; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 701; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 702; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 703; CHECK: fmr 5, 6 704; CHECK: .LBB[[BB]]: 705; CHECK: fmr 1, 5 706; CHECK: blr 707} 708 709define <4 x float> @testv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 710entry: 711 %cmp1 = fcmp oeq float %c3, %c4 712 %cmp3tmp = fcmp oeq float %c1, %c2 713 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 714 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 715 ret <4 x float> %cond 716 717; FIXME: This test (and the other v4f32 tests) should use the same bclr 718; technique as the v2f64 tests below. 719 720; CHECK-LABEL: @testv4floatslt 721; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 722; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 723; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 724; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 725; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 726; CHECK: xxlor [[REG2]], 35, 35 727; CHECK: .LBB[[BB]]: 728; CHECK: xxlor 34, [[REG2]], [[REG2]] 729; CHECK: blr 730} 731 732define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 733entry: 734 %cmp1 = fcmp oeq float %c3, %c4 735 %cmp3tmp = fcmp oeq float %c1, %c2 736 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 737 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 738 ret <4 x float> %cond 739 740; CHECK-LABEL: @testv4floatult 741; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 742; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 743; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 744; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 745; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 746; CHECK: xxlor [[REG2]], 35, 35 747; CHECK: .LBB[[BB]]: 748; CHECK: xxlor 34, [[REG2]], [[REG2]] 749; CHECK: blr 750} 751 752define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 753entry: 754 %cmp1 = fcmp oeq float %c3, %c4 755 %cmp3tmp = fcmp oeq float %c1, %c2 756 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 757 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 758 ret <4 x float> %cond 759 760; CHECK-LABEL: @testv4floatsle 761; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 762; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 763; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 764; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 765; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 766; CHECK: xxlor [[REG2]], 35, 35 767; CHECK: .LBB[[BB]]: 768; CHECK: xxlor 34, [[REG2]], [[REG2]] 769; CHECK: blr 770} 771 772define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 773entry: 774 %cmp1 = fcmp oeq float %c3, %c4 775 %cmp3tmp = fcmp oeq float %c1, %c2 776 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 777 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 778 ret <4 x float> %cond 779 780; CHECK-LABEL: @testv4floatule 781; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 782; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 783; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 784; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 785; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 786; CHECK: xxlor [[REG2]], 35, 35 787; CHECK: .LBB[[BB]]: 788; CHECK: xxlor 34, [[REG2]], [[REG2]] 789; CHECK: blr 790} 791 792define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 793entry: 794 %cmp1 = fcmp oeq float %c3, %c4 795 %cmp3tmp = fcmp oeq float %c1, %c2 796 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 797 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 798 ret <4 x float> %cond 799 800; CHECK-LABEL: @testv4floateq 801; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 802; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 803; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 804; CHECK-DAG: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 805; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 806; CHECK: xxlor [[REG2]], 35, 35 807; CHECK: .LBB[[BB]]: 808; CHECK: xxlor 34, [[REG2]], [[REG2]] 809; CHECK: blr 810} 811 812define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 813entry: 814 %cmp1 = fcmp oeq float %c3, %c4 815 %cmp3tmp = fcmp oeq float %c1, %c2 816 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 817 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 818 ret <4 x float> %cond 819 820; CHECK-LABEL: @testv4floatsge 821; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 822; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 823; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 824; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 825; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 826; CHECK: xxlor [[REG2]], 35, 35 827; CHECK: .LBB[[BB]]: 828; CHECK: xxlor 34, [[REG2]], [[REG2]] 829; CHECK: blr 830} 831 832define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 833entry: 834 %cmp1 = fcmp oeq float %c3, %c4 835 %cmp3tmp = fcmp oeq float %c1, %c2 836 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 837 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 838 ret <4 x float> %cond 839 840; CHECK-LABEL: @testv4floatuge 841; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 842; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 843; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 844; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 845; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 846; CHECK: xxlor [[REG2]], 35, 35 847; CHECK: .LBB[[BB]]: 848; CHECK: xxlor 34, [[REG2]], [[REG2]] 849; CHECK: blr 850} 851 852define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 853entry: 854 %cmp1 = fcmp oeq float %c3, %c4 855 %cmp3tmp = fcmp oeq float %c1, %c2 856 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 857 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 858 ret <4 x float> %cond 859 860; CHECK-LABEL: @testv4floatsgt 861; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 862; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 863; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 864; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 865; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 866; CHECK: xxlor [[REG2]], 35, 35 867; CHECK: .LBB[[BB]]: 868; CHECK: xxlor 34, [[REG2]], [[REG2]] 869; CHECK: blr 870} 871 872define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 873entry: 874 %cmp1 = fcmp oeq float %c3, %c4 875 %cmp3tmp = fcmp oeq float %c1, %c2 876 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 877 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 878 ret <4 x float> %cond 879 880; CHECK-LABEL: @testv4floatugt 881; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 882; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 883; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 884; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 885; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 886; CHECK: xxlor [[REG2]], 35, 35 887; CHECK: .LBB[[BB]]: 888; CHECK: xxlor 34, [[REG2]], [[REG2]] 889; CHECK: blr 890} 891 892define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 893entry: 894 %cmp1 = fcmp oeq float %c3, %c4 895 %cmp3tmp = fcmp oeq float %c1, %c2 896 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 897 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 898 ret <4 x float> %cond 899 900; CHECK-LABEL: @testv4floatne 901; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 902; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 903; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34 904; CHECK-DAG: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 905; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 906; CHECK: xxlor [[REG2]], 35, 35 907; CHECK: .LBB[[BB]]: 908; CHECK: xxlor 34, [[REG2]], [[REG2]] 909; CHECK: blr 910} 911 912define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 { 913entry: 914 %cmp1 = fcmp oeq ppc_fp128 %c3, %c4 915 %cmp3tmp = fcmp oeq ppc_fp128 %c1, %c2 916 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 917 %cond = select i1 %cmp3, ppc_fp128 %a1, ppc_fp128 %a2 918 ret ppc_fp128 %cond 919 920; FIXME: Because of the way that the late SELECT_* pseudo-instruction expansion 921; works, we end up with two blocks with the same predicate. These could be 922; combined. 923 924; CHECK-LABEL: @testppc_fp128eq 925; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8 926; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7 927; CHECK-DAG: fcmpu {{[0-9]+}}, 2, 4 928; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3 929; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 930; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 931; CHECK: creqv [[REG3:[0-9]+]], [[REG2]], [[REG1]] 932; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]] 933; CHECK: fmr 9, 11 934; CHECK: .LBB[[BB1]]: 935; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]] 936; CHECK: fmr 10, 12 937; CHECK: .LBB[[BB2]]: 938; CHECK-DAG: fmr 1, 9 939; CHECK-DAG: fmr 2, 10 940; CHECK: blr 941} 942 943define <2 x double> @testv2doubleslt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 944entry: 945 %cmp1 = fcmp oeq float %c3, %c4 946 %cmp3tmp = fcmp oeq float %c1, %c2 947 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 948 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 949 ret <2 x double> %cond 950 951; CHECK-LABEL: @testv2doubleslt 952; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 953; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 954; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 955; CHECK: bclr 12, [[REG1]], 0 956; CHECK: vor 2, 3, 3 957; CHECK: blr 958} 959 960define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 961entry: 962 %cmp1 = fcmp oeq float %c3, %c4 963 %cmp3tmp = fcmp oeq float %c1, %c2 964 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 965 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 966 ret <2 x double> %cond 967 968; CHECK-LABEL: @testv2doubleult 969; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 970; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 971; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 972; CHECK: bclr 12, [[REG1]], 0 973; CHECK: vor 2, 3, 3 974; CHECK: blr 975} 976 977define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 978entry: 979 %cmp1 = fcmp oeq float %c3, %c4 980 %cmp3tmp = fcmp oeq float %c1, %c2 981 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 982 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 983 ret <2 x double> %cond 984 985; CHECK-LABEL: @testv2doublesle 986; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 987; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 988; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 989; CHECK: bclr 12, [[REG1]], 0 990; CHECK: vor 2, 3, 3 991; CHECK: blr 992} 993 994define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 995entry: 996 %cmp1 = fcmp oeq float %c3, %c4 997 %cmp3tmp = fcmp oeq float %c1, %c2 998 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 999 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1000 ret <2 x double> %cond 1001 1002; CHECK-LABEL: @testv2doubleule 1003; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1004; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1005; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1006; CHECK: bclr 12, [[REG1]], 0 1007; CHECK: vor 2, 3, 3 1008; CHECK: blr 1009} 1010 1011define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1012entry: 1013 %cmp1 = fcmp oeq float %c3, %c4 1014 %cmp3tmp = fcmp oeq float %c1, %c2 1015 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1016 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1017 ret <2 x double> %cond 1018 1019; CHECK-LABEL: @testv2doubleeq 1020; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1021; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1022; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1023; CHECK: bclr 12, [[REG1]], 0 1024; CHECK: vor 2, 3, 3 1025; CHECK: blr 1026} 1027 1028define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1029entry: 1030 %cmp1 = fcmp oeq float %c3, %c4 1031 %cmp3tmp = fcmp oeq float %c1, %c2 1032 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1033 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1034 ret <2 x double> %cond 1035 1036; CHECK-LABEL: @testv2doublesge 1037; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1038; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1039; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1040; CHECK: bclr 12, [[REG1]], 0 1041; CHECK: vor 2, 3, 3 1042; CHECK: blr 1043} 1044 1045define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1046entry: 1047 %cmp1 = fcmp oeq float %c3, %c4 1048 %cmp3tmp = fcmp oeq float %c1, %c2 1049 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1050 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1051 ret <2 x double> %cond 1052 1053; CHECK-LABEL: @testv2doubleuge 1054; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1055; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1056; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1057; CHECK: bclr 12, [[REG1]], 0 1058; CHECK: vor 2, 3, 3 1059; CHECK: blr 1060} 1061 1062define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1063entry: 1064 %cmp1 = fcmp oeq float %c3, %c4 1065 %cmp3tmp = fcmp oeq float %c1, %c2 1066 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1067 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1068 ret <2 x double> %cond 1069 1070; CHECK-LABEL: @testv2doublesgt 1071; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1072; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1073; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1074; CHECK: bclr 12, [[REG1]], 0 1075; CHECK: vor 2, 3, 3 1076; CHECK: blr 1077} 1078 1079define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1080entry: 1081 %cmp1 = fcmp oeq float %c3, %c4 1082 %cmp3tmp = fcmp oeq float %c1, %c2 1083 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1084 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1085 ret <2 x double> %cond 1086 1087; CHECK-LABEL: @testv2doubleugt 1088; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1089; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1090; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1091; CHECK: bclr 12, [[REG1]], 0 1092; CHECK: vor 2, 3, 3 1093; CHECK: blr 1094} 1095 1096define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1097entry: 1098 %cmp1 = fcmp oeq float %c3, %c4 1099 %cmp3tmp = fcmp oeq float %c1, %c2 1100 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1101 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1102 ret <2 x double> %cond 1103 1104; CHECK-LABEL: @testv2doublene 1105; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1106; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1107; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1108; CHECK: bclr 12, [[REG1]], 0 1109; CHECK: vor 2, 3, 3 1110; CHECK: blr 1111} 1112 1113define <4 x double> @testqv4doubleslt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1114entry: 1115 %cmp1 = fcmp oeq float %c3, %c4 1116 %cmp3tmp = fcmp oeq float %c1, %c2 1117 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1118 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1119 ret <4 x double> %cond 1120 1121; CHECK-LABEL: @testqv4doubleslt 1122; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1123; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1124; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1125; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1126; CHECK: qvfmr 5, 6 1127; CHECK: .LBB[[BB]]: 1128; CHECK: qvfmr 1, 5 1129; CHECK: blr 1130} 1131 1132define <4 x double> @testqv4doubleult(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1133entry: 1134 %cmp1 = fcmp oeq float %c3, %c4 1135 %cmp3tmp = fcmp oeq float %c1, %c2 1136 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1137 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1138 ret <4 x double> %cond 1139 1140; CHECK-LABEL: @testqv4doubleult 1141; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1142; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1143; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1144; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1145; CHECK: qvfmr 5, 6 1146; CHECK: .LBB[[BB]]: 1147; CHECK: qvfmr 1, 5 1148; CHECK: blr 1149} 1150 1151define <4 x double> @testqv4doublesle(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1152entry: 1153 %cmp1 = fcmp oeq float %c3, %c4 1154 %cmp3tmp = fcmp oeq float %c1, %c2 1155 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1156 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1157 ret <4 x double> %cond 1158 1159; CHECK-LABEL: @testqv4doublesle 1160; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1161; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1162; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1163; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1164; CHECK: qvfmr 5, 6 1165; CHECK: .LBB[[BB]]: 1166; CHECK: qvfmr 1, 5 1167; CHECK: blr 1168} 1169 1170define <4 x double> @testqv4doubleule(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1171entry: 1172 %cmp1 = fcmp oeq float %c3, %c4 1173 %cmp3tmp = fcmp oeq float %c1, %c2 1174 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1175 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1176 ret <4 x double> %cond 1177 1178; CHECK-LABEL: @testqv4doubleule 1179; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1180; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1181; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1182; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1183; CHECK: qvfmr 5, 6 1184; CHECK: .LBB[[BB]]: 1185; CHECK: qvfmr 1, 5 1186; CHECK: blr 1187} 1188 1189define <4 x double> @testqv4doubleeq(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1190entry: 1191 %cmp1 = fcmp oeq float %c3, %c4 1192 %cmp3tmp = fcmp oeq float %c1, %c2 1193 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1194 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1195 ret <4 x double> %cond 1196 1197; CHECK-LABEL: @testqv4doubleeq 1198; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1199; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1200; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1201; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1202; CHECK: qvfmr 5, 6 1203; CHECK: .LBB[[BB]]: 1204; CHECK: qvfmr 1, 5 1205; CHECK: blr 1206} 1207 1208define <4 x double> @testqv4doublesge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1209entry: 1210 %cmp1 = fcmp oeq float %c3, %c4 1211 %cmp3tmp = fcmp oeq float %c1, %c2 1212 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1213 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1214 ret <4 x double> %cond 1215 1216; CHECK-LABEL: @testqv4doublesge 1217; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1218; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1219; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1220; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1221; CHECK: qvfmr 5, 6 1222; CHECK: .LBB[[BB]]: 1223; CHECK: qvfmr 1, 5 1224; CHECK: blr 1225} 1226 1227define <4 x double> @testqv4doubleuge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1228entry: 1229 %cmp1 = fcmp oeq float %c3, %c4 1230 %cmp3tmp = fcmp oeq float %c1, %c2 1231 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1232 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1233 ret <4 x double> %cond 1234 1235; CHECK-LABEL: @testqv4doubleuge 1236; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1237; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1238; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1239; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1240; CHECK: qvfmr 5, 6 1241; CHECK: .LBB[[BB]]: 1242; CHECK: qvfmr 1, 5 1243; CHECK: blr 1244} 1245 1246define <4 x double> @testqv4doublesgt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1247entry: 1248 %cmp1 = fcmp oeq float %c3, %c4 1249 %cmp3tmp = fcmp oeq float %c1, %c2 1250 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1251 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1252 ret <4 x double> %cond 1253 1254; CHECK-LABEL: @testqv4doublesgt 1255; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1256; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1257; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1258; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1259; CHECK: qvfmr 5, 6 1260; CHECK: .LBB[[BB]]: 1261; CHECK: qvfmr 1, 5 1262; CHECK: blr 1263} 1264 1265define <4 x double> @testqv4doubleugt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1266entry: 1267 %cmp1 = fcmp oeq float %c3, %c4 1268 %cmp3tmp = fcmp oeq float %c1, %c2 1269 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1270 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1271 ret <4 x double> %cond 1272 1273; CHECK-LABEL: @testqv4doubleugt 1274; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1275; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1276; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1277; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1278; CHECK: qvfmr 5, 6 1279; CHECK: .LBB[[BB]]: 1280; CHECK: qvfmr 1, 5 1281; CHECK: blr 1282} 1283 1284define <4 x double> @testqv4doublene(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1285entry: 1286 %cmp1 = fcmp oeq float %c3, %c4 1287 %cmp3tmp = fcmp oeq float %c1, %c2 1288 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1289 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1290 ret <4 x double> %cond 1291 1292; CHECK-LABEL: @testqv4doublene 1293; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1294; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1295; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1296; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1297; CHECK: qvfmr 5, 6 1298; CHECK: .LBB[[BB]]: 1299; CHECK: qvfmr 1, 5 1300; CHECK: blr 1301} 1302 1303define <4 x float> @testqv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1304entry: 1305 %cmp1 = fcmp oeq float %c3, %c4 1306 %cmp3tmp = fcmp oeq float %c1, %c2 1307 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1308 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1309 ret <4 x float> %cond 1310 1311; CHECK-LABEL: @testqv4floatslt 1312; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1313; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1314; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1315; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1316; CHECK: qvfmr 5, 6 1317; CHECK: .LBB[[BB]]: 1318; CHECK: qvfmr 1, 5 1319; CHECK: blr 1320} 1321 1322define <4 x float> @testqv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1323entry: 1324 %cmp1 = fcmp oeq float %c3, %c4 1325 %cmp3tmp = fcmp oeq float %c1, %c2 1326 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1327 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1328 ret <4 x float> %cond 1329 1330; CHECK-LABEL: @testqv4floatult 1331; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1332; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1333; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1334; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1335; CHECK: qvfmr 5, 6 1336; CHECK: .LBB[[BB]]: 1337; CHECK: qvfmr 1, 5 1338; CHECK: blr 1339} 1340 1341define <4 x float> @testqv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1342entry: 1343 %cmp1 = fcmp oeq float %c3, %c4 1344 %cmp3tmp = fcmp oeq float %c1, %c2 1345 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1346 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1347 ret <4 x float> %cond 1348 1349; CHECK-LABEL: @testqv4floatsle 1350; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1351; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1352; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1353; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1354; CHECK: qvfmr 5, 6 1355; CHECK: .LBB[[BB]]: 1356; CHECK: qvfmr 1, 5 1357; CHECK: blr 1358} 1359 1360define <4 x float> @testqv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1361entry: 1362 %cmp1 = fcmp oeq float %c3, %c4 1363 %cmp3tmp = fcmp oeq float %c1, %c2 1364 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1365 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1366 ret <4 x float> %cond 1367 1368; CHECK-LABEL: @testqv4floatule 1369; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1370; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1371; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1372; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1373; CHECK: qvfmr 5, 6 1374; CHECK: .LBB[[BB]]: 1375; CHECK: qvfmr 1, 5 1376; CHECK: blr 1377} 1378 1379define <4 x float> @testqv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1380entry: 1381 %cmp1 = fcmp oeq float %c3, %c4 1382 %cmp3tmp = fcmp oeq float %c1, %c2 1383 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1384 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1385 ret <4 x float> %cond 1386 1387; CHECK-LABEL: @testqv4floateq 1388; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1389; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1390; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1391; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1392; CHECK: qvfmr 5, 6 1393; CHECK: .LBB[[BB]]: 1394; CHECK: qvfmr 1, 5 1395; CHECK: blr 1396} 1397 1398define <4 x float> @testqv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1399entry: 1400 %cmp1 = fcmp oeq float %c3, %c4 1401 %cmp3tmp = fcmp oeq float %c1, %c2 1402 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1403 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1404 ret <4 x float> %cond 1405 1406; CHECK-LABEL: @testqv4floatsge 1407; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1408; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1409; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1410; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1411; CHECK: qvfmr 5, 6 1412; CHECK: .LBB[[BB]]: 1413; CHECK: qvfmr 1, 5 1414; CHECK: blr 1415} 1416 1417define <4 x float> @testqv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1418entry: 1419 %cmp1 = fcmp oeq float %c3, %c4 1420 %cmp3tmp = fcmp oeq float %c1, %c2 1421 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1422 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1423 ret <4 x float> %cond 1424 1425; CHECK-LABEL: @testqv4floatuge 1426; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1427; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1428; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1429; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1430; CHECK: qvfmr 5, 6 1431; CHECK: .LBB[[BB]]: 1432; CHECK: qvfmr 1, 5 1433; CHECK: blr 1434} 1435 1436define <4 x float> @testqv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1437entry: 1438 %cmp1 = fcmp oeq float %c3, %c4 1439 %cmp3tmp = fcmp oeq float %c1, %c2 1440 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1441 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1442 ret <4 x float> %cond 1443 1444; CHECK-LABEL: @testqv4floatsgt 1445; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1446; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1447; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1448; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1449; CHECK: qvfmr 5, 6 1450; CHECK: .LBB[[BB]]: 1451; CHECK: qvfmr 1, 5 1452; CHECK: blr 1453} 1454 1455define <4 x float> @testqv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1456entry: 1457 %cmp1 = fcmp oeq float %c3, %c4 1458 %cmp3tmp = fcmp oeq float %c1, %c2 1459 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1460 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1461 ret <4 x float> %cond 1462 1463; CHECK-LABEL: @testqv4floatugt 1464; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1465; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1466; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1467; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1468; CHECK: qvfmr 5, 6 1469; CHECK: .LBB[[BB]]: 1470; CHECK: qvfmr 1, 5 1471; CHECK: blr 1472} 1473 1474define <4 x float> @testqv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1475entry: 1476 %cmp1 = fcmp oeq float %c3, %c4 1477 %cmp3tmp = fcmp oeq float %c1, %c2 1478 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1479 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1480 ret <4 x float> %cond 1481 1482; CHECK-LABEL: @testqv4floatne 1483; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1484; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1485; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1486; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1487; CHECK: qvfmr 5, 6 1488; CHECK: .LBB[[BB]]: 1489; CHECK: qvfmr 1, 5 1490; CHECK: blr 1491} 1492 1493define <4 x i1> @testqv4i1slt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1494entry: 1495 %cmp1 = fcmp oeq float %c3, %c4 1496 %cmp3tmp = fcmp oeq float %c1, %c2 1497 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1498 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1499 ret <4 x i1> %cond 1500 1501; CHECK-LABEL: @testqv4i1slt 1502; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1503; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1504; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1505; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1506; CHECK: qvfmr 5, 6 1507; CHECK: .LBB[[BB]]: 1508; CHECK: qvfmr 1, 5 1509; CHECK: blr 1510} 1511 1512define <4 x i1> @testqv4i1ult(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1513entry: 1514 %cmp1 = fcmp oeq float %c3, %c4 1515 %cmp3tmp = fcmp oeq float %c1, %c2 1516 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1517 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1518 ret <4 x i1> %cond 1519 1520; CHECK-LABEL: @testqv4i1ult 1521; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1522; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1523; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1524; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1525; CHECK: qvfmr 5, 6 1526; CHECK: .LBB[[BB]]: 1527; CHECK: qvfmr 1, 5 1528; CHECK: blr 1529} 1530 1531define <4 x i1> @testqv4i1sle(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1532entry: 1533 %cmp1 = fcmp oeq float %c3, %c4 1534 %cmp3tmp = fcmp oeq float %c1, %c2 1535 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1536 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1537 ret <4 x i1> %cond 1538 1539; CHECK-LABEL: @testqv4i1sle 1540; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1541; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1542; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1543; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1544; CHECK: qvfmr 5, 6 1545; CHECK: .LBB[[BB]]: 1546; CHECK: qvfmr 1, 5 1547; CHECK: blr 1548} 1549 1550define <4 x i1> @testqv4i1ule(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1551entry: 1552 %cmp1 = fcmp oeq float %c3, %c4 1553 %cmp3tmp = fcmp oeq float %c1, %c2 1554 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1555 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1556 ret <4 x i1> %cond 1557 1558; CHECK-LABEL: @testqv4i1ule 1559; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1560; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1561; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1562; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1563; CHECK: qvfmr 5, 6 1564; CHECK: .LBB[[BB]]: 1565; CHECK: qvfmr 1, 5 1566; CHECK: blr 1567} 1568 1569define <4 x i1> @testqv4i1eq(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1570entry: 1571 %cmp1 = fcmp oeq float %c3, %c4 1572 %cmp3tmp = fcmp oeq float %c1, %c2 1573 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1574 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1575 ret <4 x i1> %cond 1576 1577; CHECK-LABEL: @testqv4i1eq 1578; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1579; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1580; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1581; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1582; CHECK: qvfmr 5, 6 1583; CHECK: .LBB[[BB]]: 1584; CHECK: qvfmr 1, 5 1585; CHECK: blr 1586} 1587 1588define <4 x i1> @testqv4i1sge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1589entry: 1590 %cmp1 = fcmp oeq float %c3, %c4 1591 %cmp3tmp = fcmp oeq float %c1, %c2 1592 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1593 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1594 ret <4 x i1> %cond 1595 1596; CHECK-LABEL: @testqv4i1sge 1597; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1598; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1599; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1600; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1601; CHECK: qvfmr 5, 6 1602; CHECK: .LBB[[BB]]: 1603; CHECK: qvfmr 1, 5 1604; CHECK: blr 1605} 1606 1607define <4 x i1> @testqv4i1uge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1608entry: 1609 %cmp1 = fcmp oeq float %c3, %c4 1610 %cmp3tmp = fcmp oeq float %c1, %c2 1611 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1612 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1613 ret <4 x i1> %cond 1614 1615; CHECK-LABEL: @testqv4i1uge 1616; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1617; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1618; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1619; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1620; CHECK: qvfmr 5, 6 1621; CHECK: .LBB[[BB]]: 1622; CHECK: qvfmr 1, 5 1623; CHECK: blr 1624} 1625 1626define <4 x i1> @testqv4i1sgt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1627entry: 1628 %cmp1 = fcmp oeq float %c3, %c4 1629 %cmp3tmp = fcmp oeq float %c1, %c2 1630 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1631 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1632 ret <4 x i1> %cond 1633 1634; CHECK-LABEL: @testqv4i1sgt 1635; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1636; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1637; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1638; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1639; CHECK: qvfmr 5, 6 1640; CHECK: .LBB[[BB]]: 1641; CHECK: qvfmr 1, 5 1642; CHECK: blr 1643} 1644 1645define <4 x i1> @testqv4i1ugt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1646entry: 1647 %cmp1 = fcmp oeq float %c3, %c4 1648 %cmp3tmp = fcmp oeq float %c1, %c2 1649 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1650 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1651 ret <4 x i1> %cond 1652 1653; CHECK-LABEL: @testqv4i1ugt 1654; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1655; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1656; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1657; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1658; CHECK: qvfmr 5, 6 1659; CHECK: .LBB[[BB]]: 1660; CHECK: qvfmr 1, 5 1661; CHECK: blr 1662} 1663 1664define <4 x i1> @testqv4i1ne(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1665entry: 1666 %cmp1 = fcmp oeq float %c3, %c4 1667 %cmp3tmp = fcmp oeq float %c1, %c2 1668 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1669 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1670 ret <4 x i1> %cond 1671 1672; CHECK-LABEL: @testqv4i1ne 1673; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1674; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1675; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1676; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] 1677; CHECK: qvfmr 5, 6 1678; CHECK: .LBB[[BB]]: 1679; CHECK: qvfmr 1, 5 1680; CHECK: blr 1681} 1682 1683attributes #0 = { nounwind readnone "target-cpu"="pwr7" } 1684attributes #1 = { nounwind readnone "target-cpu"="a2q" } 1685 1686