1; RUN: llc < %s -verify-machineinstrs -disable-fp-elim -disable-machine-dce -verify-coalescing 2target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" 3target triple = "x86_64-apple-macosx10.7.0" 4 5; This test case has a sub-register join followed by a remat: 6; 7; 256L %vreg2<def> = COPY %vreg7:sub_32bit<kill>; GR32:%vreg2 GR64:%vreg7 8; Considering merging %vreg2 with %vreg7:sub_32bit 9; Cross-class to GR64. 10; RHS = %vreg2 = [256d,272d:0) 0@256d 11; LHS = %vreg7 = [208d,256d:0)[304L,480L:0) 0@208d 12; updated: 272L %vreg0<def> = COPY %vreg7:sub_32bit<kill>; GR32:%vreg0 GR64:%vreg7 13; Joined. Result = %vreg7 = [208d,272d:0)[304L,480L:0) 0@208d 14; 15; 272L %vreg10:sub_32bit<def> = COPY %vreg7:sub_32bit<kill>, %vreg10<imp-def>; GR64:%vreg10,%vreg7 16; Considering merging %vreg7 with %vreg10 17; RHS = %vreg7 = [208d,272d:0)[304L,480L:0) 0@208d 18; LHS = %vreg10 = [16d,64L:2)[64L,160L:1)[192L,240L:1)[272d,304L:3)[304L,352d:1)[352d,400d:0)[400d,400S:4) 0@352d 1@64L-phidef 2@16d-phikill 3@272d-phikill 4@400d 19; Remat: %vreg10<def> = MOV64r0 %vreg10<imp-def>, %EFLAGS<imp-def,dead>, %vreg10<imp-def>; GR64:%vreg10 20; Shrink: %vreg7 = [208d,272d:0)[304L,480L:0) 0@208d 21; live-in at 240L 22; live-in at 416L 23; live-in at 320L 24; live-in at 304L 25; Shrunk: %vreg7 = [208d,256d:0)[304L,480L:0) 0@208d 26; 27; The COPY at 256L is rewritten as a partial def, and that would artificially 28; extend the live range of %vreg7 to end at 256d. When the joined copy is 29; removed, -verify-coalescing complains about the dangling kill. 30; 31; <rdar://problem/9967101> 32 33define void @f1() nounwind uwtable ssp { 34bb: 35 br label %bb1 36 37bb1: 38 %tmp = phi i32 [ 0, %bb ], [ %tmp21, %bb20 ] 39 br label %bb2 40 41bb2: 42 br i1 undef, label %bb5, label %bb8 43 44bb4: 45 br i1 undef, label %bb2, label %bb20 46 47bb5: 48 br i1 undef, label %bb4, label %bb20 49 50bb8: 51 %tmp9 = phi i32 [ %tmp24, %bb23 ], [ 0, %bb2 ] 52 br i1 false, label %bb41, label %bb10 53 54bb10: 55 %tmp11 = sub nsw i32 %tmp9, %tmp 56 br i1 false, label %bb2, label %bb26 57 58bb20: 59 %tmp21 = phi i32 [ undef, %bb4 ], [ undef, %bb5 ], [ %tmp9, %bb27 ], [ undef, %bb32 ] 60 %tmp22 = phi i32 [ undef, %bb4 ], [ undef, %bb5 ], [ %tmp11, %bb27 ], [ undef, %bb32 ] 61 br label %bb1 62 63bb23: 64 %tmp24 = add nsw i32 %tmp9, 1 65 br label %bb8 66 67bb26: 68 br i1 undef, label %bb27, label %bb32 69 70bb27: 71 %tmp28 = zext i32 %tmp11 to i64 72 %tmp30 = icmp eq i64 undef, %tmp28 73 br i1 %tmp30, label %bb20, label %bb27 74 75bb32: 76 br i1 undef, label %bb20, label %bb23 77 78bb41: 79 ret void 80} 81