1; RUN: opt < %s -instcombine -S | FileCheck %s 2 3declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone 4declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone 5declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone 6declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone 7declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone 8declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone 9 10declare <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8>) nounwind readnone 11declare <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8>) nounwind readnone 12declare <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8>) nounwind readnone 13declare <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32>) nounwind readnone 14declare <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16>) nounwind readnone 15declare <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16>) nounwind readnone 16 17; 18; Basic sign extension tests 19; 20 21define <4 x i32> @sse41_pmovsxbd(<16 x i8> %v) nounwind readnone { 22; CHECK-LABEL: @sse41_pmovsxbd 23; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 24; CHECK-NEXT: sext <4 x i8> %1 to <4 x i32> 25; CHECK-NEXT: ret <4 x i32> %2 26 27 %res = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %v) 28 ret <4 x i32> %res 29} 30 31define <2 x i64> @sse41_pmovsxbq(<16 x i8> %v) nounwind readnone { 32; CHECK-LABEL: @sse41_pmovsxbq 33; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <2 x i32> <i32 0, i32 1> 34; CHECK-NEXT: sext <2 x i8> %1 to <2 x i64> 35; CHECK-NEXT: ret <2 x i64> %2 36 37 %res = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %v) 38 ret <2 x i64> %res 39} 40 41define <8 x i16> @sse41_pmovsxbw(<16 x i8> %v) nounwind readnone { 42; CHECK-LABEL: @sse41_pmovsxbw 43; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 44; CHECK-NEXT: sext <8 x i8> %1 to <8 x i16> 45; CHECK-NEXT: ret <8 x i16> %2 46 47 %res = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %v) 48 ret <8 x i16> %res 49} 50 51define <2 x i64> @sse41_pmovsxdq(<4 x i32> %v) nounwind readnone { 52; CHECK-LABEL: @sse41_pmovsxdq 53; CHECK-NEXT: shufflevector <4 x i32> %v, <4 x i32> undef, <2 x i32> <i32 0, i32 1> 54; CHECK-NEXT: sext <2 x i32> %1 to <2 x i64> 55; CHECK-NEXT: ret <2 x i64> %2 56 57 %res = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %v) 58 ret <2 x i64> %res 59} 60 61define <4 x i32> @sse41_pmovsxwd(<8 x i16> %v) nounwind readnone { 62; CHECK-LABEL: @sse41_pmovsxwd 63; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 64; CHECK-NEXT: sext <4 x i16> %1 to <4 x i32> 65; CHECK-NEXT: ret <4 x i32> %2 66 67 %res = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %v) 68 ret <4 x i32> %res 69} 70 71define <2 x i64> @sse41_pmovsxwq(<8 x i16> %v) nounwind readnone { 72; CHECK-LABEL: @sse41_pmovsxwq 73; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <2 x i32> <i32 0, i32 1> 74; CHECK-NEXT: sext <2 x i16> %1 to <2 x i64> 75; CHECK-NEXT: ret <2 x i64> %2 76 77 %res = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %v) 78 ret <2 x i64> %res 79} 80 81define <8 x i32> @avx2_pmovsxbd(<16 x i8> %v) nounwind readnone { 82; CHECK-LABEL: @avx2_pmovsxbd 83; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 84; CHECK-NEXT: sext <8 x i8> %1 to <8 x i32> 85; CHECK-NEXT: ret <8 x i32> %2 86 87 %res = call <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8> %v) 88 ret <8 x i32> %res 89} 90 91define <4 x i64> @avx2_pmovsxbq(<16 x i8> %v) nounwind readnone { 92; CHECK-LABEL: @avx2_pmovsxbq 93; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 94; CHECK-NEXT: sext <4 x i8> %1 to <4 x i64> 95; CHECK-NEXT: ret <4 x i64> %2 96 97 %res = call <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8> %v) 98 ret <4 x i64> %res 99} 100 101define <16 x i16> @avx2_pmovsxbw(<16 x i8> %v) nounwind readnone { 102; CHECK-LABEL: @avx2_pmovsxbw 103; CHECK-NEXT: sext <16 x i8> %v to <16 x i16> 104; CHECK-NEXT: ret <16 x i16> %1 105 106 %res = call <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8> %v) 107 ret <16 x i16> %res 108} 109 110define <4 x i64> @avx2_pmovsxdq(<4 x i32> %v) nounwind readnone { 111; CHECK-LABEL: @avx2_pmovsxdq 112; CHECK-NEXT: sext <4 x i32> %v to <4 x i64> 113; CHECK-NEXT: ret <4 x i64> %1 114 115 %res = call <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32> %v) 116 ret <4 x i64> %res 117} 118 119define <8 x i32> @avx2_pmovsxwd(<8 x i16> %v) nounwind readnone { 120; CHECK-LABEL: @avx2_pmovsxwd 121; CHECK-NEXT: sext <8 x i16> %v to <8 x i32> 122; CHECK-NEXT: ret <8 x i32> %1 123 124 %res = call <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16> %v) 125 ret <8 x i32> %res 126} 127 128define <4 x i64> @avx2_pmovsxwq(<8 x i16> %v) nounwind readnone { 129; CHECK-LABEL: @avx2_pmovsxwq 130; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 131; CHECK-NEXT: sext <4 x i16> %1 to <4 x i64> 132; CHECK-NEXT: ret <4 x i64> %2 133 134 %res = call <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16> %v) 135 ret <4 x i64> %res 136} 137