Lines Matching refs:Rs
21 : Pat <(IntID I32:$Rs),
22 (MI I32:$Rs)>;
25 : Pat <(IntID I64:$Rs),
26 (MI DoubleRegs:$Rs)>;
33 : Pat<(IntID I32:$Rs, ImmPred:$It),
34 (MI I32:$Rs, ImmPred:$It)>;
41 : Pat<(IntID I64:$Rs, imm:$It),
42 (MI DoubleRegs:$Rs, imm:$It)>;
45 : Pat<(IntID I32:$Rs, I64:$Rt),
46 (MI I32:$Rs, DoubleRegs:$Rt)>;
49 : Pat <(IntID I32:$Rs, I32:$Rt),
50 (MI I32:$Rs, I32:$Rt)>;
53 : Pat <(IntID I64:$Rs, I64:$Rt),
54 (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
61 : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is),
62 (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>;
65 : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
66 (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
69 : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
70 (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
73 : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu),
74 (MI I32:$Rs, imm:$It, imm:$Iu)>;
77 : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu),
78 (MI imm:$It, I32:$Rs, imm:$Iu)>;
81 : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt),
82 (MI imm:$Is, I32:$Rs, I32:$Rt)>;
85 : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt),
86 (MI I32:$Rs, imm:$Is, I32:$Rt)>;
89 : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
90 (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
93 : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu),
94 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, imm:$Iu)>;
97 : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu),
98 (MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>;
101 : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru),
102 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, DoubleRegs:$Ru)>;
105 : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru),
106 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>;
109 : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
110 (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
113 : Pat <(IntID I64:$Rs, I64:$Rt, (i32 PredRegs:$Ru)),
114 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, PredRegs:$Ru)>;
117 : Pat <(IntID I64:$Rs, I32:$Rt),
118 (MI DoubleRegs:$Rs, I32:$Rt)>;
121 : Pat<(IntID (F64:$Rs)),
122 (MI (F64:$Rs))>;
126 : Pat<(IntID F64:$Rs, ImmPred:$It),
127 (MI F64:$Rs, ImmPred:$It)>;
130 : Pat<(IntID F32:$Rs),
131 (MI F32:$Rs)>;
135 : Pat<(IntID F32:$Rs, ImmPred:$It),
136 (MI F32:$Rs, ImmPred:$It)>;
139 : Pat<(IntID F32:$Rs, F32:$Rt),
140 (MI F32:$Rs, F32:$Rt)>;
143 : Pat<(IntID F64:$Rs, F64:$Rt),
144 (MI F64:$Rs, F64:$Rt)>;
147 : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru),
148 (MI F32:$Rs, F32:$Rt, F32:$Ru)>;
151 : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, (i32 PredRegs:$Rx)),
152 (MI F32:$Rs, F32:$Rt, F32:$Ru, PredRegs:$Rx)>;
156 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
208 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
301 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
459 // Rd=add(Rt.L,Rs.[HL])[:sat]
460 // Rd=sub(Rt.L,Rs.[HL])[:sat]
461 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
462 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
465 //Rd=add(Rt.L,Rs.[LH])
469 //Rd=add(Rt.L,Rs.[LH]):sat
473 //Rd=sub(Rt.L,Rs.[LH])
477 //Rd=sub(Rt.L,Rs.[LH]):sat
481 //Rd=add(Rt.[LH],Rs.[LH]):<<16
487 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
493 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
499 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
663 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
664 (A2_subri -1, IntRegs:$Rs)>;
667 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
668 (A2_subri 0, IntRegs:$Rs)>;
671 def : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
672 (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
673 def : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
674 (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
696 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs), (I32:$Rt))),
697 (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
735 // The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0.
856 def : Pat<(int_hexagon_C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
857 (C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt)>;
860 // Rdd = mpy[u](Rs, Rt)
875 // Rdd=vmpyh(Rs,Rt)[:<<1]:sat
879 // Rxx[+-]= mpy[u](Rs,Rt)
885 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
891 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
897 // Rxx+=cmpy[ir](Rs,Rt)
901 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
910 Pat<(i32 (IntID IntRegs:$Rs)),
911 (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs))))>;
914 Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt)),
915 (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs), (C2_tfrrp IntRegs:$Rt))))>;
1101 def: Pat<(i32 (int_hexagon_C2_tfrpr (I32:$Rs))),
1102 (i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>;
1103 def: Pat<(i32 (int_hexagon_C2_tfrrp (I32:$Rs))),
1104 (i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>;
1107 def: Pat<(i64 (int_hexagon_C2_mask (I32:$Rs))),
1108 (i64 (C2_mask (C2_tfrrp (I32:$Rs))))>;
1111 def: Pat<(i32 (int_hexagon_C2_vitpack (I32:$Rs), (I32:$Rt))),
1112 (i32 (C2_vitpack (C2_tfrrp (I32:$Rs)),
1260 def: Pat<(i32 (int_hexagon_S2_storew_locked (I32:$Rs), (I32:$Rt))),
1261 (i32 (C2_tfrpr (S2_storew_locked (I32:$Rs), (I32:$Rt))))>;
1262 def: Pat<(i32 (int_hexagon_S4_stored_locked (I32:$Rs), (I64:$Rt))),
1263 (i32 (C2_tfrpr (S4_stored_locked (I32:$Rs), (I64:$Rt))))>;
1270 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
1271 (MI I32:$Rs, Val:$Rt, I32:$Ru)>;
1280 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
1281 (MI I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s)>;