1//===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This is populated based on the following specs: 10// Hexagon V2 Architecture 11// Application-Level Specification 12// 80-V9418-8 Rev. B 13// March 4, 2008 14//===----------------------------------------------------------------------===// 15 16class T_I_pat <InstHexagon MI, Intrinsic IntID> 17 : Pat <(IntID imm:$Is), 18 (MI imm:$Is)>; 19 20class T_R_pat <InstHexagon MI, Intrinsic IntID> 21 : Pat <(IntID I32:$Rs), 22 (MI I32:$Rs)>; 23 24class T_P_pat <InstHexagon MI, Intrinsic IntID> 25 : Pat <(IntID I64:$Rs), 26 (MI DoubleRegs:$Rs)>; 27 28class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2> 29 : Pat<(IntID Imm1:$Is, Imm2:$It), 30 (MI Imm1:$Is, Imm2:$It)>; 31 32class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>> 33 : Pat<(IntID I32:$Rs, ImmPred:$It), 34 (MI I32:$Rs, ImmPred:$It)>; 35 36class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>> 37 : Pat<(IntID ImmPred:$Is, I32:$Rt), 38 (MI ImmPred:$Is, I32:$Rt)>; 39 40class T_PI_pat <InstHexagon MI, Intrinsic IntID> 41 : Pat<(IntID I64:$Rs, imm:$It), 42 (MI DoubleRegs:$Rs, imm:$It)>; 43 44class T_RP_pat <InstHexagon MI, Intrinsic IntID> 45 : Pat<(IntID I32:$Rs, I64:$Rt), 46 (MI I32:$Rs, DoubleRegs:$Rt)>; 47 48class T_RR_pat <InstHexagon MI, Intrinsic IntID> 49 : Pat <(IntID I32:$Rs, I32:$Rt), 50 (MI I32:$Rs, I32:$Rt)>; 51 52class T_PP_pat <InstHexagon MI, Intrinsic IntID> 53 : Pat <(IntID I64:$Rs, I64:$Rt), 54 (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>; 55 56class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2> 57 : Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It), 58 (MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>; 59 60class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred> 61 : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is), 62 (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>; 63 64class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred> 65 : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs), 66 (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>; 67 68class T_RRI_pat <InstHexagon MI, Intrinsic IntID> 69 : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu), 70 (MI I32:$Rs, I32:$Rt, imm:$Iu)>; 71 72class T_RII_pat <InstHexagon MI, Intrinsic IntID> 73 : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu), 74 (MI I32:$Rs, imm:$It, imm:$Iu)>; 75 76class T_IRI_pat <InstHexagon MI, Intrinsic IntID> 77 : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu), 78 (MI imm:$It, I32:$Rs, imm:$Iu)>; 79 80class T_IRR_pat <InstHexagon MI, Intrinsic IntID> 81 : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt), 82 (MI imm:$Is, I32:$Rs, I32:$Rt)>; 83 84class T_RIR_pat <InstHexagon MI, Intrinsic IntID> 85 : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt), 86 (MI I32:$Rs, imm:$Is, I32:$Rt)>; 87 88class T_RRR_pat <InstHexagon MI, Intrinsic IntID> 89 : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru), 90 (MI I32:$Rs, I32:$Rt, I32:$Ru)>; 91 92class T_PPI_pat <InstHexagon MI, Intrinsic IntID> 93 : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu), 94 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, imm:$Iu)>; 95 96class T_PII_pat <InstHexagon MI, Intrinsic IntID> 97 : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu), 98 (MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>; 99 100class T_PPP_pat <InstHexagon MI, Intrinsic IntID> 101 : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru), 102 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, DoubleRegs:$Ru)>; 103 104class T_PPR_pat <InstHexagon MI, Intrinsic IntID> 105 : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru), 106 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>; 107 108class T_PRR_pat <InstHexagon MI, Intrinsic IntID> 109 : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru), 110 (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>; 111 112class T_PPQ_pat <InstHexagon MI, Intrinsic IntID> 113 : Pat <(IntID I64:$Rs, I64:$Rt, (i32 PredRegs:$Ru)), 114 (MI DoubleRegs:$Rs, DoubleRegs:$Rt, PredRegs:$Ru)>; 115 116class T_PR_pat <InstHexagon MI, Intrinsic IntID> 117 : Pat <(IntID I64:$Rs, I32:$Rt), 118 (MI DoubleRegs:$Rs, I32:$Rt)>; 119 120class T_D_pat <InstHexagon MI, Intrinsic IntID> 121 : Pat<(IntID (F64:$Rs)), 122 (MI (F64:$Rs))>; 123 124class T_DI_pat <InstHexagon MI, Intrinsic IntID, 125 PatLeaf ImmPred = PatLeaf<(i32 imm)>> 126 : Pat<(IntID F64:$Rs, ImmPred:$It), 127 (MI F64:$Rs, ImmPred:$It)>; 128 129class T_F_pat <InstHexagon MI, Intrinsic IntID> 130 : Pat<(IntID F32:$Rs), 131 (MI F32:$Rs)>; 132 133class T_FI_pat <InstHexagon MI, Intrinsic IntID, 134 PatLeaf ImmPred = PatLeaf<(i32 imm)>> 135 : Pat<(IntID F32:$Rs, ImmPred:$It), 136 (MI F32:$Rs, ImmPred:$It)>; 137 138class T_FF_pat <InstHexagon MI, Intrinsic IntID> 139 : Pat<(IntID F32:$Rs, F32:$Rt), 140 (MI F32:$Rs, F32:$Rt)>; 141 142class T_DD_pat <InstHexagon MI, Intrinsic IntID> 143 : Pat<(IntID F64:$Rs, F64:$Rt), 144 (MI F64:$Rs, F64:$Rt)>; 145 146class T_FFF_pat <InstHexagon MI, Intrinsic IntID> 147 : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru), 148 (MI F32:$Rs, F32:$Rt, F32:$Ru)>; 149 150class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID> 151 : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, (i32 PredRegs:$Rx)), 152 (MI F32:$Rs, F32:$Rt, F32:$Ru, PredRegs:$Rx)>; 153 154//===----------------------------------------------------------------------===// 155// MPYS / Multipy signed/unsigned halfwords 156//Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] 157//===----------------------------------------------------------------------===// 158 159def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>; 160def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>; 161def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>; 162def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>; 163def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>; 164def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>; 165def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>; 166def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>; 167 168def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>; 169def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>; 170def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>; 171def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>; 172def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>; 173def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>; 174def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>; 175def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>; 176 177def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>; 178def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>; 179def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>; 180def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>; 181def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>; 182def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>; 183def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>; 184def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>; 185 186def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>; 187def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>; 188def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>; 189def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>; 190def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>; 191def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>; 192def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>; 193def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>; 194 195def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>; 196def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>; 197def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>; 198def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>; 199def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>; 200def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>; 201def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>; 202def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>; 203 204 205//===----------------------------------------------------------------------===// 206// MPYS / Multipy signed/unsigned halfwords and add/subtract the 207// result from the accumulator. 208//Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] 209//===----------------------------------------------------------------------===// 210 211def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>; 212def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>; 213def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>; 214def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>; 215def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>; 216def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>; 217def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>; 218def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>; 219 220def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>; 221def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>; 222def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>; 223def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>; 224def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>; 225def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>; 226def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>; 227def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>; 228 229def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>; 230def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>; 231def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>; 232def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>; 233def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>; 234def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>; 235def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>; 236def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>; 237 238def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>; 239def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>; 240def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>; 241def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>; 242def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>; 243def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>; 244def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>; 245def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>; 246 247def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>; 248def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>; 249def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>; 250def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>; 251def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>; 252def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>; 253def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>; 254def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>; 255 256def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>; 257def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>; 258def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>; 259def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>; 260def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>; 261def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>; 262def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>; 263def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>; 264 265 266//===----------------------------------------------------------------------===// 267// Multiply signed/unsigned halfwords with and without saturation and rounding 268// into a 64-bits destination register. 269//===----------------------------------------------------------------------===// 270 271def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>; 272def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>; 273def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>; 274def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>; 275def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>; 276def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>; 277def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>; 278def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>; 279 280def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>; 281def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>; 282def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>; 283def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>; 284def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>; 285def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>; 286def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>; 287def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>; 288 289def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>; 290def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>; 291def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>; 292def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>; 293def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>; 294def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>; 295def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>; 296def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>; 297 298//===----------------------------------------------------------------------===// 299// MPYS / Multipy signed/unsigned halfwords and add/subtract the 300// result from the 64-bit destination register. 301//Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] 302//===----------------------------------------------------------------------===// 303 304def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>; 305def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>; 306def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>; 307def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>; 308 309def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>; 310def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>; 311def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>; 312def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>; 313 314def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>; 315def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>; 316def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>; 317def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>; 318 319def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>; 320def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>; 321def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>; 322def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>; 323 324def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>; 325def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>; 326def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>; 327def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>; 328 329def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>; 330def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>; 331def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>; 332def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>; 333 334def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>; 335def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>; 336def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>; 337def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>; 338 339def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>; 340def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>; 341def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>; 342def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>; 343 344// Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat 345def : T_PP_pat <M2_vcmpy_s1_sat_i, int_hexagon_M2_vcmpy_s1_sat_i>; 346def : T_PP_pat <M2_vcmpy_s0_sat_i, int_hexagon_M2_vcmpy_s0_sat_i>; 347 348// Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat 349def : T_PP_pat <M2_vcmpy_s1_sat_r, int_hexagon_M2_vcmpy_s1_sat_r>; 350def : T_PP_pat <M2_vcmpy_s0_sat_r, int_hexagon_M2_vcmpy_s0_sat_r>; 351 352// Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat 353def : T_PP_pat <M2_vdmpys_s1, int_hexagon_M2_vdmpys_s1>; 354def : T_PP_pat <M2_vdmpys_s0, int_hexagon_M2_vdmpys_s0>; 355 356// Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat 357def : T_PP_pat <M2_vmpy2es_s1, int_hexagon_M2_vmpy2es_s1>; 358def : T_PP_pat <M2_vmpy2es_s0, int_hexagon_M2_vmpy2es_s0>; 359 360//Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat 361def : T_PP_pat <M2_mmpyh_s0, int_hexagon_M2_mmpyh_s0>; 362def : T_PP_pat <M2_mmpyh_s1, int_hexagon_M2_mmpyh_s1>; 363def : T_PP_pat <M2_mmpyh_rs0, int_hexagon_M2_mmpyh_rs0>; 364def : T_PP_pat <M2_mmpyh_rs1, int_hexagon_M2_mmpyh_rs1>; 365 366//Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat 367def : T_PP_pat <M2_mmpyl_s0, int_hexagon_M2_mmpyl_s0>; 368def : T_PP_pat <M2_mmpyl_s1, int_hexagon_M2_mmpyl_s1>; 369def : T_PP_pat <M2_mmpyl_rs0, int_hexagon_M2_mmpyl_rs0>; 370def : T_PP_pat <M2_mmpyl_rs1, int_hexagon_M2_mmpyl_rs1>; 371 372//Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat 373def : T_PP_pat <M2_mmpyuh_s0, int_hexagon_M2_mmpyuh_s0>; 374def : T_PP_pat <M2_mmpyuh_s1, int_hexagon_M2_mmpyuh_s1>; 375def : T_PP_pat <M2_mmpyuh_rs0, int_hexagon_M2_mmpyuh_rs0>; 376def : T_PP_pat <M2_mmpyuh_rs1, int_hexagon_M2_mmpyuh_rs1>; 377 378//Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat 379def : T_PP_pat <M2_mmpyul_s0, int_hexagon_M2_mmpyul_s0>; 380def : T_PP_pat <M2_mmpyul_s1, int_hexagon_M2_mmpyul_s1>; 381def : T_PP_pat <M2_mmpyul_rs0, int_hexagon_M2_mmpyul_rs0>; 382def : T_PP_pat <M2_mmpyul_rs1, int_hexagon_M2_mmpyul_rs1>; 383 384// Vector reduce add unsigned bytes: Rdd32[+]=vrmpybu(Rss32,Rtt32) 385def : T_PP_pat <A2_vraddub, int_hexagon_A2_vraddub>; 386def : T_PPP_pat <A2_vraddub_acc, int_hexagon_A2_vraddub_acc>; 387 388// Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt) 389def : T_PP_pat <A2_vrsadub, int_hexagon_A2_vrsadub>; 390def : T_PPP_pat <A2_vrsadub_acc, int_hexagon_A2_vrsadub_acc>; 391 392// Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss) 393def : T_PP_pat <M2_vabsdiffh, int_hexagon_M2_vabsdiffh>; 394 395// Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss) 396def : T_PP_pat <M2_vabsdiffw, int_hexagon_M2_vabsdiffw>; 397 398// Vector reduce complex multiply real or imaginary: 399// Rdd[+]=vrcmpy[ir](Rss,Rtt[*]) 400def : T_PP_pat <M2_vrcmpyi_s0, int_hexagon_M2_vrcmpyi_s0>; 401def : T_PP_pat <M2_vrcmpyi_s0c, int_hexagon_M2_vrcmpyi_s0c>; 402def : T_PPP_pat <M2_vrcmaci_s0, int_hexagon_M2_vrcmaci_s0>; 403def : T_PPP_pat <M2_vrcmaci_s0c, int_hexagon_M2_vrcmaci_s0c>; 404 405def : T_PP_pat <M2_vrcmpyr_s0, int_hexagon_M2_vrcmpyr_s0>; 406def : T_PP_pat <M2_vrcmpyr_s0c, int_hexagon_M2_vrcmpyr_s0c>; 407def : T_PPP_pat <M2_vrcmacr_s0, int_hexagon_M2_vrcmacr_s0>; 408def : T_PPP_pat <M2_vrcmacr_s0c, int_hexagon_M2_vrcmacr_s0c>; 409 410// Vector reduce halfwords 411// Rdd[+]=vrmpyh(Rss,Rtt) 412def : T_PP_pat <M2_vrmpy_s0, int_hexagon_M2_vrmpy_s0>; 413def : T_PPP_pat <M2_vrmac_s0, int_hexagon_M2_vrmac_s0>; 414 415//===----------------------------------------------------------------------===// 416// Vector Multipy with accumulation 417//===----------------------------------------------------------------------===// 418 419// Vector multiply word by signed half with accumulation 420// Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat 421def : T_PPP_pat <M2_mmacls_s1, int_hexagon_M2_mmacls_s1>; 422def : T_PPP_pat <M2_mmacls_s0, int_hexagon_M2_mmacls_s0>; 423def : T_PPP_pat <M2_mmacls_rs1, int_hexagon_M2_mmacls_rs1>; 424def : T_PPP_pat <M2_mmacls_rs0, int_hexagon_M2_mmacls_rs0>; 425def : T_PPP_pat <M2_mmachs_s1, int_hexagon_M2_mmachs_s1>; 426def : T_PPP_pat <M2_mmachs_s0, int_hexagon_M2_mmachs_s0>; 427def : T_PPP_pat <M2_mmachs_rs1, int_hexagon_M2_mmachs_rs1>; 428def : T_PPP_pat <M2_mmachs_rs0, int_hexagon_M2_mmachs_rs0>; 429 430// Vector multiply word by unsigned half with accumulation 431// Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat 432def : T_PPP_pat <M2_mmaculs_s1, int_hexagon_M2_mmaculs_s1>; 433def : T_PPP_pat <M2_mmaculs_s0, int_hexagon_M2_mmaculs_s0>; 434def : T_PPP_pat <M2_mmaculs_rs1, int_hexagon_M2_mmaculs_rs1>; 435def : T_PPP_pat <M2_mmaculs_rs0, int_hexagon_M2_mmaculs_rs0>; 436def : T_PPP_pat <M2_mmacuhs_s1, int_hexagon_M2_mmacuhs_s1>; 437def : T_PPP_pat <M2_mmacuhs_s0, int_hexagon_M2_mmacuhs_s0>; 438def : T_PPP_pat <M2_mmacuhs_rs1, int_hexagon_M2_mmacuhs_rs1>; 439def : T_PPP_pat <M2_mmacuhs_rs0, int_hexagon_M2_mmacuhs_rs0>; 440 441// Vector multiply even halfwords with accumulation 442// Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat] 443def : T_PPP_pat <M2_vmac2es, int_hexagon_M2_vmac2es>; 444def : T_PPP_pat <M2_vmac2es_s1, int_hexagon_M2_vmac2es_s1>; 445def : T_PPP_pat <M2_vmac2es_s0, int_hexagon_M2_vmac2es_s0>; 446 447// Vector dual multiply with accumulation 448// Rxx+=vdmpy(Rss,Rtt)[:sat] 449def : T_PPP_pat <M2_vdmacs_s1, int_hexagon_M2_vdmacs_s1>; 450def : T_PPP_pat <M2_vdmacs_s0, int_hexagon_M2_vdmacs_s0>; 451 452// Vector complex multiply real or imaginary with accumulation 453// Rxx+=vcmpy[ir](Rss,Rtt):sat 454def : T_PPP_pat <M2_vcmac_s0_sat_r, int_hexagon_M2_vcmac_s0_sat_r>; 455def : T_PPP_pat <M2_vcmac_s0_sat_i, int_hexagon_M2_vcmac_s0_sat_i>; 456 457//===----------------------------------------------------------------------===// 458// Add/Subtract halfword 459// Rd=add(Rt.L,Rs.[HL])[:sat] 460// Rd=sub(Rt.L,Rs.[HL])[:sat] 461// Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16] 462// Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16] 463//===----------------------------------------------------------------------===// 464 465//Rd=add(Rt.L,Rs.[LH]) 466def : T_RR_pat <A2_addh_l16_ll, int_hexagon_A2_addh_l16_ll>; 467def : T_RR_pat <A2_addh_l16_hl, int_hexagon_A2_addh_l16_hl>; 468 469//Rd=add(Rt.L,Rs.[LH]):sat 470def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>; 471def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>; 472 473//Rd=sub(Rt.L,Rs.[LH]) 474def : T_RR_pat <A2_subh_l16_ll, int_hexagon_A2_subh_l16_ll>; 475def : T_RR_pat <A2_subh_l16_hl, int_hexagon_A2_subh_l16_hl>; 476 477//Rd=sub(Rt.L,Rs.[LH]):sat 478def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>; 479def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>; 480 481//Rd=add(Rt.[LH],Rs.[LH]):<<16 482def : T_RR_pat <A2_addh_h16_ll, int_hexagon_A2_addh_h16_ll>; 483def : T_RR_pat <A2_addh_h16_lh, int_hexagon_A2_addh_h16_lh>; 484def : T_RR_pat <A2_addh_h16_hl, int_hexagon_A2_addh_h16_hl>; 485def : T_RR_pat <A2_addh_h16_hh, int_hexagon_A2_addh_h16_hh>; 486 487//Rd=sub(Rt.[LH],Rs.[LH]):<<16 488def : T_RR_pat <A2_subh_h16_ll, int_hexagon_A2_subh_h16_ll>; 489def : T_RR_pat <A2_subh_h16_lh, int_hexagon_A2_subh_h16_lh>; 490def : T_RR_pat <A2_subh_h16_hl, int_hexagon_A2_subh_h16_hl>; 491def : T_RR_pat <A2_subh_h16_hh, int_hexagon_A2_subh_h16_hh>; 492 493//Rd=add(Rt.[LH],Rs.[LH]):sat:<<16 494def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>; 495def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>; 496def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>; 497def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>; 498 499//Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16 500def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>; 501def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>; 502def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>; 503def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>; 504 505// ALU64 / ALU / min max 506def : T_RR_pat<A2_max, int_hexagon_A2_max>; 507def : T_RR_pat<A2_min, int_hexagon_A2_min>; 508def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>; 509def : T_RR_pat<A2_minu, int_hexagon_A2_minu>; 510 511// Shift and accumulate 512def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>; 513def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>; 514def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>; 515def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>; 516def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>; 517def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>; 518 519def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>; 520def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>; 521def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>; 522def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>; 523def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>; 524def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>; 525def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>; 526def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>; 527 528def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>; 529def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>; 530def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>; 531def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>; 532def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>; 533def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>; 534 535def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>; 536def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>; 537def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>; 538def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>; 539def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>; 540def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>; 541def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>; 542def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>; 543 544def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>; 545def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>; 546def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>; 547def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>; 548def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>; 549def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>; 550def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>; 551def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>; 552 553def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>; 554def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>; 555def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>; 556def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>; 557def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>; 558def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>; 559def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>; 560def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>; 561 562def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>; 563def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>; 564def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>; 565def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>; 566def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>; 567def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>; 568def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>; 569def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>; 570 571def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>; 572def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>; 573def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>; 574def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>; 575def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>; 576def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>; 577def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>; 578def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>; 579 580def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>; 581def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>; 582def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>; 583def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>; 584def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>; 585def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>; 586 587def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>; 588def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>; 589def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>; 590def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>; 591def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>; 592def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>; 593def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>; 594def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>; 595 596def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>; 597def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>; 598def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>; 599def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>; 600def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>; 601def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>; 602 603def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>; 604def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>; 605def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>; 606def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>; 607def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>; 608def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>; 609def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>; 610def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>; 611 612def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>; 613def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>; 614def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>; 615def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>; 616def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>; 617def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>; 618def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>; 619def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>; 620 621def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>; 622def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>; 623def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>; 624def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>; 625def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>; 626def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>; 627def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>; 628def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>; 629 630def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>; 631def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>; 632def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>; 633def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>; 634def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>; 635def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>; 636def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>; 637def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>; 638 639def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>; 640def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>; 641def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>; 642def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>; 643def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>; 644def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>; 645def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>; 646def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>; 647 648/******************************************************************** 649* ALU32/ALU * 650*********************************************************************/ 651def : T_RR_pat<A2_add, int_hexagon_A2_add>; 652def : T_RI_pat<A2_addi, int_hexagon_A2_addi>; 653def : T_RR_pat<A2_sub, int_hexagon_A2_sub>; 654def : T_IR_pat<A2_subri, int_hexagon_A2_subri>; 655def : T_RR_pat<A2_and, int_hexagon_A2_and>; 656def : T_RI_pat<A2_andir, int_hexagon_A2_andir>; 657def : T_RR_pat<A2_or, int_hexagon_A2_or>; 658def : T_RI_pat<A2_orir, int_hexagon_A2_orir>; 659def : T_RR_pat<A2_xor, int_hexagon_A2_xor>; 660def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>; 661 662// Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32) 663def : Pat <(int_hexagon_A2_not (I32:$Rs)), 664 (A2_subri -1, IntRegs:$Rs)>; 665 666// Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32) 667def : Pat <(int_hexagon_A2_neg IntRegs:$Rs), 668 (A2_subri 0, IntRegs:$Rs)>; 669 670// Transfer immediate 671def : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is), 672 (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>; 673def : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is), 674 (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>; 675 676// Transfer Register/immediate. 677def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>; 678def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>; 679def : T_I_pat <A2_tfrpi, int_hexagon_A2_tfrpi>; 680 681// Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32) 682def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src), 683 (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>; 684 685/******************************************************************** 686* ALU32/PERM * 687*********************************************************************/ 688// Combine 689def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>; 690def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>; 691def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>; 692def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>; 693 694def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s32ImmPred, s8ImmPred>; 695 696def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs), (I32:$Rt))), 697 (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>; 698 699// Mux 700def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s32ImmPred>; 701def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s32ImmPred>; 702def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s32ImmPred, s8ImmPred>; 703 704// Shift halfword 705def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>; 706def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>; 707def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>; 708 709// Sign/zero extend 710def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>; 711def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>; 712def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>; 713def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>; 714 715/******************************************************************** 716* ALU32/PRED * 717*********************************************************************/ 718// Compare 719def : T_RR_pat<C2_cmpeq, int_hexagon_C2_cmpeq>; 720def : T_RR_pat<C2_cmpgt, int_hexagon_C2_cmpgt>; 721def : T_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>; 722 723def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s32ImmPred>; 724def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s32ImmPred>; 725def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u32ImmPred>; 726 727def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s32ImmPred:$src2)), 728 (i32 (C2_cmpgti (I32:$src1), 729 (DEC_CONST_SIGNED s32ImmPred:$src2)))>; 730 731def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u32ImmPred:$src2)), 732 (i32 (C2_cmpgtui (I32:$src1), 733 (DEC_CONST_UNSIGNED u32ImmPred:$src2)))>; 734 735// The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0. 736def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)), 737 (i32 (C2_cmpeq (I32:$src1), (I32:$src1)))>; 738 739def : Pat <(i32 (int_hexagon_C2_cmplt (I32:$src1), 740 (I32:$src2))), 741 (i32 (C2_cmpgt (I32:$src2), (I32:$src1)))>; 742 743def : Pat <(i32 (int_hexagon_C2_cmpltu (I32:$src1), 744 (I32:$src2))), 745 (i32 (C2_cmpgtu (I32:$src2), (I32:$src1)))>; 746 747/******************************************************************** 748* ALU32/VH * 749*********************************************************************/ 750// Vector add, subtract, average halfwords 751def: T_RR_pat<A2_svaddh, int_hexagon_A2_svaddh>; 752def: T_RR_pat<A2_svaddhs, int_hexagon_A2_svaddhs>; 753def: T_RR_pat<A2_svadduhs, int_hexagon_A2_svadduhs>; 754 755def: T_RR_pat<A2_svsubh, int_hexagon_A2_svsubh>; 756def: T_RR_pat<A2_svsubhs, int_hexagon_A2_svsubhs>; 757def: T_RR_pat<A2_svsubuhs, int_hexagon_A2_svsubuhs>; 758 759def: T_RR_pat<A2_svavgh, int_hexagon_A2_svavgh>; 760def: T_RR_pat<A2_svavghs, int_hexagon_A2_svavghs>; 761def: T_RR_pat<A2_svnavgh, int_hexagon_A2_svnavgh>; 762 763/******************************************************************** 764* ALU64/ALU * 765*********************************************************************/ 766def: T_RR_pat<A2_addsat, int_hexagon_A2_addsat>; 767def: T_RR_pat<A2_subsat, int_hexagon_A2_subsat>; 768def: T_PP_pat<A2_addp, int_hexagon_A2_addp>; 769def: T_PP_pat<A2_subp, int_hexagon_A2_subp>; 770 771def: T_PP_pat<A2_andp, int_hexagon_A2_andp>; 772def: T_PP_pat<A2_orp, int_hexagon_A2_orp>; 773def: T_PP_pat<A2_xorp, int_hexagon_A2_xorp>; 774 775def: T_PP_pat<C2_cmpeqp, int_hexagon_C2_cmpeqp>; 776def: T_PP_pat<C2_cmpgtp, int_hexagon_C2_cmpgtp>; 777def: T_PP_pat<C2_cmpgtup, int_hexagon_C2_cmpgtup>; 778 779def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>; 780def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>; 781 782/******************************************************************** 783* ALU64/VB * 784*********************************************************************/ 785// ALU64 - Vector add 786def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddub>; 787def : T_PP_pat <A2_vaddubs, int_hexagon_A2_vaddubs>; 788def : T_PP_pat <A2_vaddh, int_hexagon_A2_vaddh>; 789def : T_PP_pat <A2_vaddhs, int_hexagon_A2_vaddhs>; 790def : T_PP_pat <A2_vadduhs, int_hexagon_A2_vadduhs>; 791def : T_PP_pat <A2_vaddw, int_hexagon_A2_vaddw>; 792def : T_PP_pat <A2_vaddws, int_hexagon_A2_vaddws>; 793 794// ALU64 - Vector average 795def : T_PP_pat <A2_vavgub, int_hexagon_A2_vavgub>; 796def : T_PP_pat <A2_vavgubr, int_hexagon_A2_vavgubr>; 797def : T_PP_pat <A2_vavgh, int_hexagon_A2_vavgh>; 798def : T_PP_pat <A2_vavghr, int_hexagon_A2_vavghr>; 799def : T_PP_pat <A2_vavghcr, int_hexagon_A2_vavghcr>; 800def : T_PP_pat <A2_vavguh, int_hexagon_A2_vavguh>; 801def : T_PP_pat <A2_vavguhr, int_hexagon_A2_vavguhr>; 802 803def : T_PP_pat <A2_vavgw, int_hexagon_A2_vavgw>; 804def : T_PP_pat <A2_vavgwr, int_hexagon_A2_vavgwr>; 805def : T_PP_pat <A2_vavgwcr, int_hexagon_A2_vavgwcr>; 806def : T_PP_pat <A2_vavguw, int_hexagon_A2_vavguw>; 807def : T_PP_pat <A2_vavguwr, int_hexagon_A2_vavguwr>; 808 809// ALU64 - Vector negative average 810def : T_PP_pat <A2_vnavgh, int_hexagon_A2_vnavgh>; 811def : T_PP_pat <A2_vnavghr, int_hexagon_A2_vnavghr>; 812def : T_PP_pat <A2_vnavghcr, int_hexagon_A2_vnavghcr>; 813def : T_PP_pat <A2_vnavgw, int_hexagon_A2_vnavgw>; 814def : T_PP_pat <A2_vnavgwr, int_hexagon_A2_vnavgwr>; 815def : T_PP_pat <A2_vnavgwcr, int_hexagon_A2_vnavgwcr>; 816 817// ALU64 - Vector max 818def : T_PP_pat <A2_vmaxh, int_hexagon_A2_vmaxh>; 819def : T_PP_pat <A2_vmaxw, int_hexagon_A2_vmaxw>; 820def : T_PP_pat <A2_vmaxub, int_hexagon_A2_vmaxub>; 821def : T_PP_pat <A2_vmaxuh, int_hexagon_A2_vmaxuh>; 822def : T_PP_pat <A2_vmaxuw, int_hexagon_A2_vmaxuw>; 823 824// ALU64 - Vector min 825def : T_PP_pat <A2_vminh, int_hexagon_A2_vminh>; 826def : T_PP_pat <A2_vminw, int_hexagon_A2_vminw>; 827def : T_PP_pat <A2_vminub, int_hexagon_A2_vminub>; 828def : T_PP_pat <A2_vminuh, int_hexagon_A2_vminuh>; 829def : T_PP_pat <A2_vminuw, int_hexagon_A2_vminuw>; 830 831// ALU64 - Vector sub 832def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubub>; 833def : T_PP_pat <A2_vsububs, int_hexagon_A2_vsububs>; 834def : T_PP_pat <A2_vsubh, int_hexagon_A2_vsubh>; 835def : T_PP_pat <A2_vsubhs, int_hexagon_A2_vsubhs>; 836def : T_PP_pat <A2_vsubuhs, int_hexagon_A2_vsubuhs>; 837def : T_PP_pat <A2_vsubw, int_hexagon_A2_vsubw>; 838def : T_PP_pat <A2_vsubws, int_hexagon_A2_vsubws>; 839 840// ALU64 - Vector compare bytes 841def : T_PP_pat <A2_vcmpbeq, int_hexagon_A2_vcmpbeq>; 842def : T_PP_pat <A4_vcmpbgt, int_hexagon_A4_vcmpbgt>; 843def : T_PP_pat <A2_vcmpbgtu, int_hexagon_A2_vcmpbgtu>; 844 845// ALU64 - Vector compare halfwords 846def : T_PP_pat <A2_vcmpheq, int_hexagon_A2_vcmpheq>; 847def : T_PP_pat <A2_vcmphgt, int_hexagon_A2_vcmphgt>; 848def : T_PP_pat <A2_vcmphgtu, int_hexagon_A2_vcmphgtu>; 849 850// ALU64 - Vector compare words 851def : T_PP_pat <A2_vcmpweq, int_hexagon_A2_vcmpweq>; 852def : T_PP_pat <A2_vcmpwgt, int_hexagon_A2_vcmpwgt>; 853def : T_PP_pat <A2_vcmpwgtu, int_hexagon_A2_vcmpwgtu>; 854 855// ALU64 / VB / Vector mux. 856def : Pat<(int_hexagon_C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), 857 (C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt)>; 858 859// MPY - Multiply and use full result 860// Rdd = mpy[u](Rs, Rt) 861def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>; 862def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>; 863 864// Complex multiply real or imaginary 865def : T_RR_pat <M2_cmpyi_s0, int_hexagon_M2_cmpyi_s0>; 866def : T_RR_pat <M2_cmpyr_s0, int_hexagon_M2_cmpyr_s0>; 867 868// Complex multiply 869def : T_RR_pat <M2_cmpys_s0, int_hexagon_M2_cmpys_s0>; 870def : T_RR_pat <M2_cmpysc_s0, int_hexagon_M2_cmpysc_s0>; 871def : T_RR_pat <M2_cmpys_s1, int_hexagon_M2_cmpys_s1>; 872def : T_RR_pat <M2_cmpysc_s1, int_hexagon_M2_cmpysc_s1>; 873 874// Vector multiply halfwords 875// Rdd=vmpyh(Rs,Rt)[:<<1]:sat 876def : T_RR_pat <M2_vmpy2s_s0, int_hexagon_M2_vmpy2s_s0>; 877def : T_RR_pat <M2_vmpy2s_s1, int_hexagon_M2_vmpy2s_s1>; 878 879// Rxx[+-]= mpy[u](Rs,Rt) 880def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>; 881def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>; 882def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>; 883def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>; 884 885// Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat 886def : T_PRR_pat <M2_cmacs_s0, int_hexagon_M2_cmacs_s0>; 887def : T_PRR_pat <M2_cnacs_s0, int_hexagon_M2_cnacs_s0>; 888def : T_PRR_pat <M2_cmacs_s1, int_hexagon_M2_cmacs_s1>; 889def : T_PRR_pat <M2_cnacs_s1, int_hexagon_M2_cnacs_s1>; 890 891// Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat 892def : T_PRR_pat <M2_cmacsc_s0, int_hexagon_M2_cmacsc_s0>; 893def : T_PRR_pat <M2_cnacsc_s0, int_hexagon_M2_cnacsc_s0>; 894def : T_PRR_pat <M2_cmacsc_s1, int_hexagon_M2_cmacsc_s1>; 895def : T_PRR_pat <M2_cnacsc_s1, int_hexagon_M2_cnacsc_s1>; 896 897// Rxx+=cmpy[ir](Rs,Rt) 898def : T_PRR_pat <M2_cmaci_s0, int_hexagon_M2_cmaci_s0>; 899def : T_PRR_pat <M2_cmacr_s0, int_hexagon_M2_cmacr_s0>; 900 901// Rxx+=vmpyh(Rs,Rt)[:<<1][:sat] 902def : T_PRR_pat <M2_vmac2, int_hexagon_M2_vmac2>; 903def : T_PRR_pat <M2_vmac2s_s0, int_hexagon_M2_vmac2s_s0>; 904def : T_PRR_pat <M2_vmac2s_s1, int_hexagon_M2_vmac2s_s1>; 905 906/******************************************************************** 907* CR * 908*********************************************************************/ 909class qi_CRInst_qi_pat<InstHexagon Inst, Intrinsic IntID> : 910 Pat<(i32 (IntID IntRegs:$Rs)), 911 (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs))))>; 912 913class qi_CRInst_qiqi_pat<InstHexagon Inst, Intrinsic IntID> : 914 Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt)), 915 (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs), (C2_tfrrp IntRegs:$Rt))))>; 916 917def: qi_CRInst_qi_pat<C2_not, int_hexagon_C2_not>; 918def: qi_CRInst_qi_pat<C2_all8, int_hexagon_C2_all8>; 919def: qi_CRInst_qi_pat<C2_any8, int_hexagon_C2_any8>; 920 921def: qi_CRInst_qiqi_pat<C2_and, int_hexagon_C2_and>; 922def: qi_CRInst_qiqi_pat<C2_andn, int_hexagon_C2_andn>; 923def: qi_CRInst_qiqi_pat<C2_or, int_hexagon_C2_or>; 924def: qi_CRInst_qiqi_pat<C2_orn, int_hexagon_C2_orn>; 925def: qi_CRInst_qiqi_pat<C2_xor, int_hexagon_C2_xor>; 926 927// Assembler mapped from Pd4=Ps4 to Pd4=or(Ps4,Ps4) 928def : Pat<(int_hexagon_C2_pxfer_map PredRegs:$src), 929 (C2_pxfer_map PredRegs:$src)>; 930 931// Multiply 32x32 and use lower result 932def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>; 933def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>; 934def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>; 935 936// Subtract and accumulate 937def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>; 938 939// Add and accumulate 940def : T_RRR_pat <M2_acci, int_hexagon_M2_acci>; 941def : T_RRR_pat <M2_nacci, int_hexagon_M2_nacci>; 942def : T_RRI_pat <M2_accii, int_hexagon_M2_accii>; 943def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>; 944 945// XOR and XOR with destination 946def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>; 947 948class MType_R32_pat <Intrinsic IntID, InstHexagon OutputInst> : 949 Pat <(IntID IntRegs:$src1, IntRegs:$src2), 950 (OutputInst IntRegs:$src1, IntRegs:$src2)>; 951 952// Vector dual multiply with round and pack 953 954def : Pat <(int_hexagon_M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2), 955 (M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2)>; 956 957def : Pat <(int_hexagon_M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2), 958 (M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2)>; 959 960// Vector multiply halfwords with round and pack 961 962def : MType_R32_pat <int_hexagon_M2_vmpy2s_s0pack, M2_vmpy2s_s0pack>; 963def : MType_R32_pat <int_hexagon_M2_vmpy2s_s1pack, M2_vmpy2s_s1pack>; 964 965// Multiply and use lower result 966def : MType_R32_pat <int_hexagon_M2_mpyi, M2_mpyi>; 967def : T_RI_pat<M2_mpysmi, int_hexagon_M2_mpysmi>; 968 969// Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32) 970def : MType_R32_pat <int_hexagon_M2_mpyui, M2_mpyi>; 971 972// Multiply and use upper result 973def : MType_R32_pat <int_hexagon_M2_mpy_up, M2_mpy_up>; 974def : MType_R32_pat <int_hexagon_M2_mpyu_up, M2_mpyu_up>; 975def : MType_R32_pat <int_hexagon_M2_hmmpyh_rs1, M2_hmmpyh_rs1>; 976def : MType_R32_pat <int_hexagon_M2_hmmpyl_rs1, M2_hmmpyl_rs1>; 977def : MType_R32_pat <int_hexagon_M2_dpmpyss_rnd_s0, M2_dpmpyss_rnd_s0>; 978 979// Complex multiply with round and pack 980// Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat 981def : MType_R32_pat <int_hexagon_M2_cmpyrs_s0, M2_cmpyrs_s0>; 982def : MType_R32_pat <int_hexagon_M2_cmpyrs_s1, M2_cmpyrs_s1>; 983def : MType_R32_pat <int_hexagon_M2_cmpyrsc_s0, M2_cmpyrsc_s0>; 984def : MType_R32_pat <int_hexagon_M2_cmpyrsc_s1, M2_cmpyrsc_s1>; 985 986/******************************************************************** 987* STYPE/ALU * 988*********************************************************************/ 989def : T_P_pat <A2_absp, int_hexagon_A2_absp>; 990def : T_P_pat <A2_negp, int_hexagon_A2_negp>; 991def : T_P_pat <A2_notp, int_hexagon_A2_notp>; 992 993/******************************************************************** 994* STYPE/BIT * 995*********************************************************************/ 996 997// Count leading/trailing 998def: T_R_pat<S2_cl0, int_hexagon_S2_cl0>; 999def: T_P_pat<S2_cl0p, int_hexagon_S2_cl0p>; 1000def: T_R_pat<S2_cl1, int_hexagon_S2_cl1>; 1001def: T_P_pat<S2_cl1p, int_hexagon_S2_cl1p>; 1002def: T_R_pat<S2_clb, int_hexagon_S2_clb>; 1003def: T_P_pat<S2_clbp, int_hexagon_S2_clbp>; 1004def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>; 1005def: T_R_pat<S2_ct0, int_hexagon_S2_ct0>; 1006def: T_R_pat<S2_ct1, int_hexagon_S2_ct1>; 1007 1008// Compare bit mask 1009def: T_RR_pat<C2_bitsclr, int_hexagon_C2_bitsclr>; 1010def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>; 1011def: T_RR_pat<C2_bitsset, int_hexagon_C2_bitsset>; 1012 1013// Vector shuffle 1014def : T_PP_pat <S2_shuffeb, int_hexagon_S2_shuffeb>; 1015def : T_PP_pat <S2_shuffob, int_hexagon_S2_shuffob>; 1016def : T_PP_pat <S2_shuffeh, int_hexagon_S2_shuffeh>; 1017def : T_PP_pat <S2_shuffoh, int_hexagon_S2_shuffoh>; 1018 1019// Vector truncate 1020def : T_PP_pat <S2_vtrunewh, int_hexagon_S2_vtrunewh>; 1021def : T_PP_pat <S2_vtrunowh, int_hexagon_S2_vtrunowh>; 1022 1023// Linear feedback-shift Iteration. 1024def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>; 1025 1026// Vector splice 1027def : T_PPQ_pat <S2_vsplicerb, int_hexagon_S2_vsplicerb>; 1028def : T_PPI_pat <S2_vspliceib, int_hexagon_S2_vspliceib>; 1029 1030// Shift by immediate and add 1031def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>; 1032 1033// Extract bitfield 1034def : T_PII_pat<S2_extractup, int_hexagon_S2_extractup>; 1035def : T_RII_pat<S2_extractu, int_hexagon_S2_extractu>; 1036def : T_RP_pat <S2_extractu_rp, int_hexagon_S2_extractu_rp>; 1037def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>; 1038 1039// Insert bitfield 1040def : Pat <(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2, 1041 DoubleRegs:$src3), 1042 (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>; 1043 1044def : Pat<(i64 (int_hexagon_S2_insertp_rp (I64:$src1), 1045 (I64:$src2), (I64:$src3))), 1046 (i64 (S2_insertp_rp (I64:$src1), (I64:$src2), 1047 (I64:$src3)))>; 1048 1049def : Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2, 1050 u5ImmPred:$src3, u5ImmPred:$src4), 1051 (S2_insert IntRegs:$src1, IntRegs:$src2, 1052 u5ImmPred:$src3, u5ImmPred:$src4)>; 1053 1054def : Pat<(i64 (int_hexagon_S2_insertp (I64:$src1), 1055 (I64:$src2), u6ImmPred:$src3, u6ImmPred:$src4)), 1056 (i64 (S2_insertp (I64:$src1), (I64:$src2), 1057 u6ImmPred:$src3, u6ImmPred:$src4))>; 1058 1059 1060// Innterleave/deinterleave 1061def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>; 1062def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>; 1063 1064// Set/Clear/Toggle Bit 1065def: T_RI_pat<S2_setbit_i, int_hexagon_S2_setbit_i>; 1066def: T_RI_pat<S2_clrbit_i, int_hexagon_S2_clrbit_i>; 1067def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>; 1068 1069def: T_RR_pat<S2_setbit_r, int_hexagon_S2_setbit_r>; 1070def: T_RR_pat<S2_clrbit_r, int_hexagon_S2_clrbit_r>; 1071def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>; 1072 1073// Test Bit 1074def: T_RI_pat<S2_tstbit_i, int_hexagon_S2_tstbit_i>; 1075def: T_RR_pat<S2_tstbit_r, int_hexagon_S2_tstbit_r>; 1076 1077/******************************************************************** 1078* STYPE/COMPLEX * 1079*********************************************************************/ 1080// Vector Complex conjugate 1081def : T_P_pat <A2_vconj, int_hexagon_A2_vconj>; 1082 1083// Vector Complex rotate 1084def : T_PR_pat <S2_vcrotate, int_hexagon_S2_vcrotate>; 1085 1086/******************************************************************** 1087* STYPE/PERM * 1088*********************************************************************/ 1089 1090// Vector saturate without pack 1091def : T_P_pat <S2_vsathb_nopack, int_hexagon_S2_vsathb_nopack>; 1092def : T_P_pat <S2_vsathub_nopack, int_hexagon_S2_vsathub_nopack>; 1093def : T_P_pat <S2_vsatwh_nopack, int_hexagon_S2_vsatwh_nopack>; 1094def : T_P_pat <S2_vsatwuh_nopack, int_hexagon_S2_vsatwuh_nopack>; 1095 1096/******************************************************************** 1097* STYPE/PRED * 1098*********************************************************************/ 1099 1100// Predicate transfer 1101def: Pat<(i32 (int_hexagon_C2_tfrpr (I32:$Rs))), 1102 (i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>; 1103def: Pat<(i32 (int_hexagon_C2_tfrrp (I32:$Rs))), 1104 (i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>; 1105 1106// Mask generate from predicate 1107def: Pat<(i64 (int_hexagon_C2_mask (I32:$Rs))), 1108 (i64 (C2_mask (C2_tfrrp (I32:$Rs))))>; 1109 1110// Viterbi pack even and odd predicate bits 1111def: Pat<(i32 (int_hexagon_C2_vitpack (I32:$Rs), (I32:$Rt))), 1112 (i32 (C2_vitpack (C2_tfrrp (I32:$Rs)), 1113 (C2_tfrrp (I32:$Rt))))>; 1114 1115/******************************************************************** 1116* STYPE/SHIFT * 1117*********************************************************************/ 1118 1119def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>; 1120def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>; 1121def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>; 1122 1123def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>; 1124def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>; 1125def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>; 1126def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>; 1127 1128def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>; 1129def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>; 1130def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>; 1131def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>; 1132 1133def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>; 1134def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>; 1135 1136def : T_R_pat <S2_vsxtbh, int_hexagon_S2_vsxtbh>; 1137def : T_R_pat <S2_vzxtbh, int_hexagon_S2_vzxtbh>; 1138def : T_R_pat <S2_vsxthw, int_hexagon_S2_vsxthw>; 1139def : T_R_pat <S2_vzxthw, int_hexagon_S2_vzxthw>; 1140def : T_R_pat <S2_vsplatrh, int_hexagon_S2_vsplatrh>; 1141def : T_R_pat <A2_sxtw, int_hexagon_A2_sxtw>; 1142 1143// Vector saturate and pack 1144def : T_R_pat <S2_svsathb, int_hexagon_S2_svsathb>; 1145def : T_R_pat <S2_svsathub, int_hexagon_S2_svsathub>; 1146def : T_P_pat <S2_vsathub, int_hexagon_S2_vsathub>; 1147def : T_P_pat <S2_vsatwh, int_hexagon_S2_vsatwh>; 1148def : T_P_pat <S2_vsatwuh, int_hexagon_S2_vsatwuh>; 1149def : T_P_pat <S2_vsathb, int_hexagon_S2_vsathb>; 1150 1151def : T_P_pat <S2_vtrunohb, int_hexagon_S2_vtrunohb>; 1152def : T_P_pat <S2_vtrunehb, int_hexagon_S2_vtrunehb>; 1153def : T_P_pat <S2_vrndpackwh, int_hexagon_S2_vrndpackwh>; 1154def : T_P_pat <S2_vrndpackwhs, int_hexagon_S2_vrndpackwhs>; 1155def : T_R_pat <S2_brev, int_hexagon_S2_brev>; 1156def : T_R_pat <S2_vsplatrb, int_hexagon_S2_vsplatrb>; 1157 1158def : T_R_pat <A2_abs, int_hexagon_A2_abs>; 1159def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>; 1160def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>; 1161 1162def : T_R_pat <A2_swiz, int_hexagon_A2_swiz>; 1163 1164def : T_P_pat <A2_sat, int_hexagon_A2_sat>; 1165def : T_R_pat <A2_sath, int_hexagon_A2_sath>; 1166def : T_R_pat <A2_satuh, int_hexagon_A2_satuh>; 1167def : T_R_pat <A2_satub, int_hexagon_A2_satub>; 1168def : T_R_pat <A2_satb, int_hexagon_A2_satb>; 1169 1170// Vector arithmetic shift right by immediate with truncate and pack. 1171def : T_PI_pat<S2_asr_i_svw_trun, int_hexagon_S2_asr_i_svw_trun>; 1172 1173def : T_RI_pat <S2_asr_i_r, int_hexagon_S2_asr_i_r>; 1174def : T_RI_pat <S2_lsr_i_r, int_hexagon_S2_lsr_i_r>; 1175def : T_RI_pat <S2_asl_i_r, int_hexagon_S2_asl_i_r>; 1176def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>; 1177def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax, 1178 int_hexagon_S2_asr_i_r_rnd_goodsyntax>; 1179 1180// Shift left by immediate with saturation. 1181def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>; 1182 1183//===----------------------------------------------------------------------===// 1184// Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions. 1185//===----------------------------------------------------------------------===// 1186class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst, 1187 SDNodeXForm XformImm> 1188 : Pat <(IntID IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3, u5ImmPred:$src4), 1189 (OutputInst IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3, 1190 (XformImm u5ImmPred:$src4))>; 1191 1192 1193// Table Index : Extract and insert bits. 1194// Map to the real hardware instructions after subtracting appropriate 1195// values from the 4th input operand. Please note that subtraction is not 1196// needed for int_hexagon_S2_tableidxb_goodsyntax. 1197 1198def : Pat <(int_hexagon_S2_tableidxb_goodsyntax IntRegs:$src1, IntRegs:$src2, 1199 u4ImmPred:$src3, u5ImmPred:$src4), 1200 (S2_tableidxb IntRegs:$src1, IntRegs:$src2, 1201 u4ImmPred:$src3, u5ImmPred:$src4)>; 1202 1203def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh, 1204 DEC_CONST_SIGNED>; 1205def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw, 1206 DEC2_CONST_SIGNED>; 1207def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd, 1208 DEC3_CONST_SIGNED>; 1209 1210/******************************************************************** 1211* STYPE/VH * 1212*********************************************************************/ 1213 1214// Vector absolute value halfwords with and without saturation 1215// Rdd64=vabsh(Rss64)[:sat] 1216def : T_P_pat <A2_vabsh, int_hexagon_A2_vabsh>; 1217def : T_P_pat <A2_vabshsat, int_hexagon_A2_vabshsat>; 1218 1219// Vector shift halfwords by immediate 1220// Rdd64=[vaslh/vasrh/vlsrh](Rss64,u4) 1221def : T_PI_pat <S2_asr_i_vh, int_hexagon_S2_asr_i_vh>; 1222def : T_PI_pat <S2_lsr_i_vh, int_hexagon_S2_lsr_i_vh>; 1223def : T_PI_pat <S2_asl_i_vh, int_hexagon_S2_asl_i_vh>; 1224 1225// Vector shift halfwords by register 1226// Rdd64=[vaslw/vasrw/vlslw/vlsrw](Rss64,Rt32) 1227def : T_PR_pat <S2_asr_r_vh, int_hexagon_S2_asr_r_vh>; 1228def : T_PR_pat <S2_lsr_r_vh, int_hexagon_S2_lsr_r_vh>; 1229def : T_PR_pat <S2_asl_r_vh, int_hexagon_S2_asl_r_vh>; 1230def : T_PR_pat <S2_lsl_r_vh, int_hexagon_S2_lsl_r_vh>; 1231 1232/******************************************************************** 1233* STYPE/VW * 1234*********************************************************************/ 1235 1236// Vector absolute value words with and without saturation 1237def : T_P_pat <A2_vabsw, int_hexagon_A2_vabsw>; 1238def : T_P_pat <A2_vabswsat, int_hexagon_A2_vabswsat>; 1239 1240// Vector shift words by immediate. 1241// Rdd64=[vasrw/vlsrw|vaslw](Rss64,u5) 1242def : T_PI_pat <S2_asr_i_vw, int_hexagon_S2_asr_i_vw>; 1243def : T_PI_pat <S2_lsr_i_vw, int_hexagon_S2_lsr_i_vw>; 1244def : T_PI_pat <S2_asl_i_vw, int_hexagon_S2_asl_i_vw>; 1245 1246// Vector shift words by register. 1247// Rdd64=[vasrw/vlsrw|vaslw|vlslw](Rss64,Rt32) 1248def : T_PR_pat <S2_asr_r_vw, int_hexagon_S2_asr_r_vw>; 1249def : T_PR_pat <S2_lsr_r_vw, int_hexagon_S2_lsr_r_vw>; 1250def : T_PR_pat <S2_asl_r_vw, int_hexagon_S2_asl_r_vw>; 1251def : T_PR_pat <S2_lsl_r_vw, int_hexagon_S2_lsl_r_vw>; 1252 1253// Vector shift words with truncate and pack 1254 1255def : T_PR_pat <S2_asr_r_svw_trun, int_hexagon_S2_asr_r_svw_trun>; 1256 1257def : T_R_pat<L2_loadw_locked, int_hexagon_L2_loadw_locked>; 1258def : T_R_pat<L4_loadd_locked, int_hexagon_L4_loadd_locked>; 1259 1260def: Pat<(i32 (int_hexagon_S2_storew_locked (I32:$Rs), (I32:$Rt))), 1261 (i32 (C2_tfrpr (S2_storew_locked (I32:$Rs), (I32:$Rt))))>; 1262def: Pat<(i32 (int_hexagon_S4_stored_locked (I32:$Rs), (I64:$Rt))), 1263 (i32 (C2_tfrpr (S4_stored_locked (I32:$Rs), (I64:$Rt))))>; 1264 1265/******************************************************************** 1266* ST 1267*********************************************************************/ 1268 1269class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val> 1270 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru), 1271 (MI I32:$Rs, Val:$Rt, I32:$Ru)>; 1272 1273def : T_stb_pat <S2_storerh_pbr_pseudo, int_hexagon_brev_sth, I32>; 1274def : T_stb_pat <S2_storerb_pbr_pseudo, int_hexagon_brev_stb, I32>; 1275def : T_stb_pat <S2_storeri_pbr_pseudo, int_hexagon_brev_stw, I32>; 1276def : T_stb_pat <S2_storerf_pbr_pseudo, int_hexagon_brev_sthhi, I32>; 1277def : T_stb_pat <S2_storerd_pbr_pseudo, int_hexagon_brev_std, I64>; 1278 1279class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val> 1280 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s), 1281 (MI I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s)>; 1282 1283def: T_stc_pat<S2_storerb_pci_pseudo, int_hexagon_circ_stb, s4_0ImmPred, I32>; 1284def: T_stc_pat<S2_storerh_pci_pseudo, int_hexagon_circ_sth, s4_1ImmPred, I32>; 1285def: T_stc_pat<S2_storeri_pci_pseudo, int_hexagon_circ_stw, s4_2ImmPred, I32>; 1286def: T_stc_pat<S2_storerd_pci_pseudo, int_hexagon_circ_std, s4_3ImmPred, I64>; 1287def: T_stc_pat<S2_storerf_pci_pseudo, int_hexagon_circ_sthhi, s4_1ImmPred, I32>; 1288 1289include "HexagonIntrinsicsV3.td" 1290include "HexagonIntrinsicsV4.td" 1291include "HexagonIntrinsicsV5.td" 1292include "HexagonIntrinsicsV60.td" 1293 1294