Home
last modified time | relevance | path

Searched defs:RC (Results 1 – 25 of 165) sorted by relevance

1234567

/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp82 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in mask() local
210 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
217 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
218 -> BT::RegisterCell { in evaluate()
227 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
262 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
278 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
283 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
299 RegisterCell RC = eADD(eSXT(CW, W1), rc(2)); in evaluate() local
308 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate() local
[all …]
DHexagonBitSimplify.cpp288 bool HexagonBitSimplify::isConst(const BitTracker::RegisterCell &RC, in isConst()
298 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, in isZero()
308 bool HexagonBitSimplify::getConst(const BitTracker::RegisterCell &RC, in getConst()
379 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg); in getSubregMask() local
867 auto *RC = MRI.getRegClass(RR.Reg); in getFinalVRegClass() local
1216 const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI); in computeUsedBits() local
1341 const BitTracker::RegisterCell &RC = BT.lookup(R); in isConst() local
1375 unsigned ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C, in genTfrConst()
1508 const BitTracker::RegisterCell &RC = BT.lookup(R); in findMatch() local
1708 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf()
[all …]
DBitTracker.cpp105 raw_ostream &llvm::operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { in operator <<()
184 bool BT::RegisterCell::meet(const RegisterCell &RC, unsigned SelfR) { in meet()
198 BT::RegisterCell &BT::RegisterCell::insert(const BT::RegisterCell &RC, in insert()
224 RegisterCell RC(E-B+1); in extract() local
230 RegisterCell RC(E+(W-B)+1); in extract() local
270 BT::RegisterCell &BT::RegisterCell::cat(const RegisterCell &RC) { in cat()
332 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PhysS); in getRegBitWidth() local
366 void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC, in putCell()
1000 void BT::put(RegisterRef RR, const RegisterCell &RC) { in put()
1017 RegisterCell &RC = I->second; in subst() local
/external/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp41 const TargetRegisterClass *RC = in getGlobalBaseReg() local
62 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; in getMips16SPAliasReg() local
68 const TargetRegisterClass *RC = in createEhDataRegsFI() local
83 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in createISRRegFI() local
106 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
DMipsSEFrameLowering.cpp156 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
171 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
189 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
214 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
246 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
295 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
358 const TargetRegisterClass *RC = in expandExtractElementF64() local
397 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
697 const TargetRegisterClass *RC = in emitEpilogue() local
814 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
[all …]
DMipsInstrInfo.h92 const TargetRegisterClass *RC, in storeRegToStackSlot()
100 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h70 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
119 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
127 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
/external/llvm/include/llvm/IR/
DIRBuilder.h766 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
780 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
788 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
802 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
810 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
824 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
832 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
844 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
856 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
863 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
[all …]
/external/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createLRSpillSlot() local
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createFPSpillSlot() local
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createEHSpillSlot() local
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h142 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
147 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
154 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
159 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
481 const TargetRegisterClass *RC) const { in getMatchingSuperReg()
516 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg()
644 getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
653 getLargestLegalSuperClass(const TargetRegisterClass *RC, in getLargestLegalSuperClass()
666 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
850 const TargetRegisterClass *RC, in saveScavengerRegister()
/external/llvm/lib/CodeGen/
DLiveStackAnalysis.cpp60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
84 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
DTargetRegisterInfo.cpp142 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass() local
155 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
193 const TargetRegisterClass *RC = in firstCommonClass() local
267 const TargetRegisterClass *RC = in getCommonSuperRegClass() local
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp450 const TargetRegisterClass *RC, in PPCEmitLoad()
596 const TargetRegisterClass *RC = in SelectLoad() local
612 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
975 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1038 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1082 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1172 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1334 const TargetRegisterClass *RC = in processCallArgs() local
1346 const TargetRegisterClass *RC = in processCallArgs() local
1660 const TargetRegisterClass *RC = in SelectRet() local
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp116 for (const auto &RC : RegisterClasses) in runEnums() local
182 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
957 for (const auto &RC : RegisterClasses) { in runMCDesc() local
997 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1110 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1147 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1156 for (const auto &RC : RegisterClasses) in runTargetDesc() local
1210 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1237 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1252 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
[all …]
DCodeGenRegisters.cpp856 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
878 for (auto &RC : RegClasses) { in computeSubClasses() local
894 for (auto &RC : RegClasses) in computeSubClasses() local
996 for (auto *RC : RCs) { in CodeGenRegBank() local
1007 for (auto &RC : RegClasses) in CodeGenRegBank() local
1037 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { in addToMaps()
1049 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, in getOrCreateSubClass()
1065 if (CodeGenRegisterClass *RC = Def2RC[Def]) in getRegClass() local
1604 for (auto &RC : RegClasses) { in computeRegUnitSets() local
1709 for (auto &RC : RegClasses) { in computeRegUnitSets() local
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIInsertWaits.cpp165 const TargetRegisterClass *RC = TII->getOpRegClass(MI, 0); in getHwCounts() local
237 RegInterval SIInsertWaits::getRegInterval(const TargetRegisterClass *RC, in getRegInterval()
305 const TargetRegisterClass *RC = TII->getOpRegClass(*I, i); in pushInstruction() local
411 const TargetRegisterClass *RC = TII->getOpRegClass(MI, i); in handleOperands() local
/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp73 const TargetRegisterClass *RC, in storeRegToStackSlot()
99 const TargetRegisterClass *RC, in loadRegFromStackSlot()
DARMFastISel.cpp285 const TargetRegisterClass *RC, in fastEmitInst_r()
307 const TargetRegisterClass *RC, in fastEmitInst_rr()
335 const TargetRegisterClass *RC, in fastEmitInst_rrr()
367 const TargetRegisterClass *RC, in fastEmitInst_ri()
393 const TargetRegisterClass *RC, in fastEmitInst_rri()
423 const TargetRegisterClass *RC, in fastEmitInst_i()
519 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
535 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
585 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass in ARMMaterializeGV() local
718 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca() local
[all …]
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp48 const TargetRegisterClass *RC, in storeRegToStackSlot()
66 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/clang/test/CodeGenCXX/
Ddevirtualize-virtual-function-calls-final.cpp187 struct RC final : public RA { struct
188 virtual C *f() { in f()
194 virtual C *operator-() { in operator -()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp352 const TargetRegisterClass *RC = nullptr; in X86FastEmitLoad() local
631 const TargetRegisterClass *RC = nullptr; in handleConstantAddresses() local
1530 const TargetRegisterClass *RC = nullptr; in X86SelectShift() local
1614 const TargetRegisterClass *RC; in X86SelectDivRem() member
1773 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect() local
1949 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect() local
2043 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect() local
2071 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect() local
2112 const TargetRegisterClass *RC = nullptr; in X86SelectSIToFP() local
2138 const TargetRegisterClass *RC) { in X86SelectFPExtOrFPTrunc()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp369 const TargetRegisterClass *RC = *I; in regPressureDelta() local
376 const TargetRegisterClass *RC = *I; in regPressureDelta() local
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
500 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp204 const MCRegisterClass &RC = MRI.getRegClass(RCID); in encodeInstruction() local
266 const MCRegisterClass &RC = MRI.getRegClass(RCID); in getMachineOpValue() local
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp40 const TargetRegisterClass *RC, in storeRegToStackSlot()
67 const TargetRegisterClass *RC, in loadRegFromStackSlot()

1234567