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Searched defs:VT (Results 1 – 25 of 146) sorted by relevance

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/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp66 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSLDUPMask()
74 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSHDUPMask()
82 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVDDUPMask()
96 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSLLDQMask()
110 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSRLDQMask()
125 void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask()
146 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSHUFMask()
163 void DecodePSHUFHWMask(MVT VT, unsigned Imm, in DecodePSHUFHWMask()
179 void DecodePSHUFLWMask(MVT VT, unsigned Imm, in DecodePSHUFLWMask()
195 void DecodePSWAPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodePSWAPMask()
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/external/llvm/lib/CodeGen/
DCallingConvLower.cpp93 MVT VT = Outs[i].VT; in CheckReturn() local
107 MVT VT = Outs[i].VT; in AnalyzeReturn() local
160 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
173 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
183 static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) { in isValueTypeInRegForCC()
194 MVT VT, CCAssignFn Fn) { in getRemainingRegParmsForType()
DTargetLoweringBase.cpp656 RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) { in getATOMIC()
774 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
1033 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT()
1273 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1385 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, in getVectorTypeBreakdown()
1463 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1509 const DataLayout &DL, EVT VT, in allowsMemoryAccess()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h66 TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { in getTypeAction()
71 bool isTypeLegal(EVT VT) const { in isTypeLegal()
76 bool isSimpleLegalType(EVT VT) const { in isSimpleLegalType()
84 bool isLegalInHWReg(EVT VT) const { in isLegalInHWReg()
89 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
DLegalizeVectorOps.cpp402 MVT VT = Op.getSimpleValueType(); in Promote() local
435 EVT VT = Op.getOperand(0).getValueType(); in PromoteINT_TO_FP() local
471 EVT VT = Op.getValueType(); in PromoteFP_TO_INT() local
731 EVT VT = Op.getValueType(); in ExpandSELECT() local
786 EVT VT = Op.getValueType(); in ExpandSEXTINREG() local
809 EVT VT = Op.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
832 EVT VT = Op.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
856 EVT VT = Op.getValueType(); in ExpandZERO_EXTEND_VECTOR_INREG() local
885 EVT VT = Op.getValueType(); in ExpandBSWAP() local
908 EVT VT = Op.getValueType(); in ExpandBITREVERSE() local
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DSelectionDAG.cpp80 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
705 EVT VT = N->getValueType(0); in VerifySDNode() local
780 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1011 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getAnyExtOrTrunc()
1017 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getSExtOrTrunc()
1023 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getZExtOrTrunc()
1029 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, in getBoolExtOrTrunc()
1038 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, SDLoc DL, EVT VT) { in getZeroExtendInReg()
1050 SDValue SelectionDAG::getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) { in getAnyExtendVectorInReg()
1060 SDValue SelectionDAG::getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) { in getSignExtendVectorInReg()
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DDAGCombiner.cpp485 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
826 EVT VT = N0.getValueType(); in ReassociateOps() local
947 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
1038 EVT VT = Op.getValueType(); in PromoteIntBinOp() local
1096 EVT VT = Op.getValueType(); in PromoteIntShiftOp() local
1140 EVT VT = Op.getValueType(); in PromoteExtend() local
1169 EVT VT = Op.getValueType(); in PromoteLoad() local
1641 EVT VT = N0.getValueType(); in visitADD() local
1794 EVT VT = N0.getValueType(); in visitADDC() local
1853 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT, in tryFoldToZero()
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DResourcePriorityQueue.cpp96 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
134 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() local
334 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
343 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() local
486 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
497 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode() local
DLegalizeDAG.cpp217 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, in ShuffleWithNarrowerEltType()
257 EVT VT = CFP->getValueType(0); in ExpandConstantFP() local
301 EVT VT = CP->getValueType(0); in ExpandConstant() local
321 EVT VT = Val.getValueType(); in ExpandUnalignedStore() local
448 EVT VT = LD->getValueType(0); in ExpandUnalignedLoad() local
610 EVT VT = Tmp1.getValueType(); in PerformInsertVectorEltInMemory() local
747 MVT VT = Value.getSimpleValueType(); in LegalizeStoreOps() local
907 MVT VT = Node->getSimpleValueType(0); in LegalizeLoadOps() local
1582 EVT VT = Node->getValueType(0); in ExpandVectorBuildThroughStack() local
1773 EVT VT = Node->getValueType(0); in ExpandDYNAMIC_STACKALLOC() local
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DLegalizeFloatTypes.cpp30 static RTLIB::Libcall GetFPLibCall(EVT VT, in GetFPLibCall()
613 EVT VT = N->getValueType(0); in SoftenFloatRes_LOAD() local
674 EVT VT = N->getValueType(0); in SoftenFloatRes_VAARG() local
849 EVT VT = NewLHS.getValueType(); in SoftenFloatOp_BR_CC() local
901 EVT VT = NewLHS.getValueType(); in SoftenFloatOp_SELECT_CC() local
924 EVT VT = NewLHS.getValueType(); in SoftenFloatOp_SETCC() local
1389 EVT VT = N->getValueType(0); in ExpandFloatRes_XINT_TO_FP() local
1775 EVT VT = N->getValueType(0); in PromoteFloatOp_FP_EXTEND() local
1800 EVT VT = N->getValueType(0); in PromoteFloatOp_SETCC() local
1818 EVT VT = ST->getOperand(1)->getValueType(0); in PromoteFloatOp_STORE() local
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/external/llvm/include/llvm/Target/
DTargetLowering.h207 getPreferredVectorAction(EVT VT) const { in getPreferredVectorAction()
234 virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const { in isIntDivCheap()
329 virtual bool enableAggressiveFMAFusion(EVT VT) const { in enableAggressiveFMAFusion()
380 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor()
393 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor()
400 virtual uint8_t getRepRegClassCostFor(MVT VT) const { in getRepRegClassCostFor()
407 bool isTypeLegal(EVT VT) const { in isTypeLegal()
424 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
428 void setTypeAction(MVT VT, LegalizeTypeAction Action) { in setTypeAction()
441 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { in getTypeAction()
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/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp47 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
57 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) { in getEquivalentLoadRegType()
184 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
190 for (MVT VT : MVT::integer_vector_valuetypes()) { in AMDGPUTargetLowering() local
241 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering() local
295 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering() local
340 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering() local
696 EVT VT = EVT::getEVT(InitTy); in LowerConstantInitializer() local
704 EVT VT = EVT::getEVT(CFP->getType()); in LowerConstantInitializer() local
734 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy)) in LowerConstantInitializer() local
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DSIISelLowering.cpp135 for (MVT VT : MVT::integer_valuetypes()) { in SITargetLowering() local
155 for (MVT VT : MVT::integer_vector_valuetypes()) { in SITargetLowering() local
160 for (MVT VT : MVT::fp_valuetypes()) in SITargetLowering() local
434 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT, in allowsMisalignedMemoryAccesses()
537 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, in LowerParameter()
686 MVT VT = VA.getLocVT(); in LowerFormalArguments() local
1136 MVT VT, in lowerImplicitZextParam()
1153 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
1320 EVT VT = Op.getOperand(3).getValueType(); in LowerINTRINSIC_VOID() local
1414 EVT VT = Op.getValueType(); in LowerFastFDIV() local
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/external/llvm/lib/Target/X86/
DX86FastISel.cpp319 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { in isTypeLegal()
347 bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, in X86FastEmitLoad()
433 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, in X86FastEmitStore()
523 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, in X86FastEmitStore()
978 MVT VT; in X86SelectStore() local
1134 MVT VT; in X86SelectLoad() local
1158 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { in X86ChooseCmpOpcode()
1178 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { in X86ChooseCmpImmediateOpcode()
1206 EVT VT, DebugLoc CurDbgLoc) { in X86FastEmitCompare()
1241 MVT VT; in X86SelectCmp() local
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DX86ISelLowering.cpp139 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering() local
684 for (MVT VT : MVT::vector_valuetypes()) { in X86TargetLowering() local
888 for (MVT VT : MVT::integer_vector_valuetypes()) { in X86TargetLowering() local
949 for (MVT VT : MVT::fp_vector_valuetypes()) in X86TargetLowering() local
984 for (MVT VT : MVT::integer_vector_valuetypes()) { in X86TargetLowering() local
1115 for (MVT VT : MVT::fp_vector_valuetypes()) in X86TargetLowering() local
1266 for (MVT VT : MVT::vector_valuetypes()) { in X86TargetLowering() local
1318 for (MVT VT : MVT::fp_vector_valuetypes()) in X86TargetLowering() local
1575 for (MVT VT : MVT::vector_valuetypes()) { in X86TargetLowering() local
2015 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT, in allowsMisalignedMemoryAccesses()
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/external/llvm/include/llvm/CodeGen/
DMachineValueType.h525 bool bitsGT(MVT VT) const { in bitsGT()
530 bool bitsGE(MVT VT) const { in bitsGE()
535 bool bitsLT(MVT VT) const { in bitsLT()
540 bool bitsLE(MVT VT) const { in bitsLE()
581 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
666 SimpleValueType VT; member
/external/mesa3d/src/gallium/drivers/radeon/
DR600ISelLowering.cpp277 EVT VT = Op.getValueType(); in LowerOperation() local
357 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, in LowerImplicitParameter()
377 EVT VT = Op.getValueType(); in LowerROTL() local
390 EVT VT = Op.getValueType(); in LowerSELECT_CC() local
DAMDGPUISelLowering.cpp106 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
154 EVT VT = Op.getValueType(); in LowerIntrinsicIABS() local
167 EVT VT = Op.getValueType(); in LowerIntrinsicLRP() local
184 EVT VT = Op.getValueType(); in LowerUDIVREM() local
DSIISelLowering.cpp272 EVT VT = Op.getValueType(); in LowerOperation() local
334 EVT VT = Op.getValueType(); in LowerLOAD() local
381 EVT VT = Op.getValueType(); in LowerSELECT_CC() local
396 EVT VT = N->getValueType(0); in PerformDAGCombine() local
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp88 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, in addTypeForNEON()
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
444 for (MVT VT : MVT::vector_valuetypes()) { in ARMTargetLowering() local
633 for (MVT VT : MVT::integer_vector_valuetypes()) { in ARMTargetLowering() local
688 for (MVT VT : MVT::fp_valuetypes()) { in ARMTargetLowering() local
699 for (MVT VT : MVT::integer_valuetypes()) in ARMTargetLowering() local
752 for (MVT VT : MVT::vector_valuetypes()) { in ARMTargetLowering() local
1283 EVT VT = N->getValueType(i); in getSchedulingPreference() local
3440 EVT VT = Op.getValueType(); in LowerXALUO() local
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DARMFastISel.cpp443 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) { in ARMMoveToFPReg()
453 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) { in ARMMoveToIntReg()
466 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { in ARMMaterializeFP()
509 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { in ARMMaterializeInt()
579 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { in ARMMaterializeGV()
690 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
708 MVT VT; in fastMaterializeAlloca() local
732 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
744 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
861 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { in ARMSimplifyAddress()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp218 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
240 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
430 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering() local
436 for (MVT VT : MVT::integer_valuetypes()) in AArch64TargetLowering() local
597 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
631 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) { in addTypeForNEON()
715 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
720 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
757 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); in computeKnownBitsForTargetNode() local
777 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); in computeKnownBitsForTargetNode() local
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DAArch64ISelDAGToDAG.cpp1021 EVT VT = N->getValueType(0); in SelectTable() local
1043 EVT VT = LD->getMemoryVT(); in SelectIndexedLoad() local
1137 EVT VT = N->getValueType(0); in SelectLoad() local
1158 EVT VT = N->getValueType(0); in SelectPostLoad() local
1190 EVT VT = N->getOperand(2)->getValueType(0); in SelectStore() local
1206 EVT VT = N->getOperand(2)->getValueType(0); in SelectPostStore() local
1234 EVT VT = V64Reg.getValueType(); in operator ()() local
1250 EVT VT = V128Reg.getValueType(); in NarrowVector() local
1262 EVT VT = N->getValueType(0); in SelectLoadLane() local
1302 EVT VT = N->getValueType(0); in SelectPostLoadLane() local
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/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.h47 EVT VT) const override { in isShuffleMaskLegal()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp265 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
279 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
418 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, in PPCSimplifyAddress()
449 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in PPCEmitLoad()
583 MVT VT; in SelectLoad() local
607 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) { in PPCEmitStore()
728 MVT VT; in SelectStore() local
1060 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT, in PPCMoveToIntReg()
1886 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) { in PPCMaterializeFP()
1937 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) { in PPCMaterializeGV()
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