| /external/llvm/test/CodeGen/X86/ |
| D | rotate.ll | 4 define i32 @rotl32(i32 %A, i8 %Amt) {
5 %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
7 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
14 define i32 @rotr32(i32 %A, i8 %Amt) {
15 %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
17 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
38 define i16 @rotl16(i16 %A, i8 %Amt) {
39 %shift.upgrd.5 = zext i8 %Amt to i16 ; <i16> [#uses=1]
41 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
48 define i16 @rotr16(i16 %A, i8 %Amt) {
[all …]
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| D | legalize-shl-vec.ll | 4 %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
5 %Out = shl <2 x i256> %In, %Amt
21 %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
22 %Out = lshr <2 x i256> %In, %Amt
38 %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
39 %Out = ashr <2 x i256> %In, %Amt
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | rotl-2.ll | 6 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
7 %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
9 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
16 define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
17 %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
19 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
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| D | rotl-64.ll | 12 define i64 @t2(i64 %A, i8 zeroext %Amt) {
13 %Amt1 = zext i8 %Amt to i64
15 %Amt2 = sub i8 64, %Amt
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 86 static inline unsigned rotr32(unsigned Val, unsigned Amt) { in rotr32() argument
87 assert(Amt < 32 && "Invalid rotate amount"); in rotr32()
88 return (Val >> Amt) | (Val << ((32-Amt)&31)); in rotr32()
93 static inline unsigned rotl32(unsigned Val, unsigned Amt) { in rotl32() argument
94 assert(Amt < 32 && "Invalid rotate amount"); in rotl32()
95 return (Val << Amt) | (Val >> ((32-Amt)&31)); in rotl32()
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| D | BasicValueFactory.cpp | 182 uint64_t Amt = V2.getZExtValue(); in evalAPSInt() local
184 if (Amt >= V1.getBitWidth()) in evalAPSInt()
187 return &getValue( V1.operator<<( (unsigned) Amt )); in evalAPSInt()
200 uint64_t Amt = V2.getZExtValue(); in evalAPSInt() local
202 if (Amt >= V1.getBitWidth()) in evalAPSInt()
205 return &getValue( V1.operator>>( (unsigned) Amt )); in evalAPSInt()
|
| /external/clang/lib/Analysis/ |
| D | FormatString.cpp | 82 const OptionalAmount &Amt = ParseAmount(I, E); in ParsePositionAmount() local
84 if (Amt.getHowSpecified() == OptionalAmount::NotSpecified) { in ParsePositionAmount()
95 assert(Amt.getHowSpecified() == OptionalAmount::Constant); in ParsePositionAmount()
101 if (Amt.getConstantAmount() == 0) { in ParsePositionAmount()
109 return OptionalAmount(OptionalAmount::Arg, Amt.getConstantAmount() - 1, in ParsePositionAmount()
132 const OptionalAmount Amt = in ParseFieldWidth() local
136 if (Amt.isInvalid()) in ParseFieldWidth()
138 CS.setFieldWidth(Amt); in ParseFieldWidth()
151 const OptionalAmount &Amt = ParseAmount(I, E); in ParseArgPosition() local
159 if (Amt.getHowSpecified() == OptionalAmount::Constant && *(I++) == '$') { in ParseArgPosition()
[all …]
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| D | ScanfFormatString.cpp | 133 const OptionalAmount &Amt = clang::analyze_format_string::ParseAmount(I, E); in ParseScanfSpecifier() local
134 if (Amt.getHowSpecified() != OptionalAmount::NotSpecified) { in ParseScanfSpecifier()
135 assert(Amt.getHowSpecified() == OptionalAmount::Constant); in ParseScanfSpecifier()
136 FS.setFieldWidth(Amt); in ParseScanfSpecifier()
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| D | PrintfFormatString.cpp | 43 const OptionalAmount Amt = ParsePositionAmount(H, Start, Beg, E, in ParsePrecision() local
45 if (Amt.isInvalid()) in ParsePrecision()
47 FS.setPrecision(Amt); in ParsePrecision()
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| /external/llvm/include/llvm/ADT/ |
| D | APSInt.h | 124 APSInt operator>>(unsigned Amt) const {
125 return IsUnsigned ? APSInt(lshr(Amt), true) : APSInt(ashr(Amt), false);
127 APSInt& operator>>=(unsigned Amt) {
128 *this = *this >> Amt;
181 APSInt& operator<<=(unsigned Amt) {
182 *this = *this << Amt;
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| D | APInt.h | 956 APInt sshl_ov(const APInt &Amt, bool &Overflow) const;
957 APInt ushl_ov(const APInt &Amt, bool &Overflow) const;
|
| /external/llvm/test/CodeGen/Generic/ |
| D | shift-int64.ll | 8 define i64 @test_variable(i64 %X, i8 %Amt) {
9 %shift.upgrd.1 = zext i8 %Amt to i64 ; <i64> [#uses=1]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 1412 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt, in ExpandShiftByConstant() argument
1421 if (!Amt) { in ExpandShiftByConstant()
1433 if (Amt.ugt(VTBits)) { in ExpandShiftByConstant()
1435 } else if (Amt.ugt(NVTBits)) { in ExpandShiftByConstant()
1438 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy)); in ExpandShiftByConstant()
1439 } else if (Amt == NVTBits) { in ExpandShiftByConstant()
1442 } else if (Amt == 1 && in ExpandShiftByConstant()
1452 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy)); in ExpandShiftByConstant()
1455 DAG.getConstant(Amt, DL, ShTy)), in ExpandShiftByConstant()
1457 DAG.getConstant(-Amt + NVTBits, DL, ShTy))); in ExpandShiftByConstant()
[all …]
|
| /external/llvm/include/llvm/IR/ |
| D | BasicBlock.h | 324 void AdjustBlockAddressRefCount(int Amt) {
325 setValueSubclassData(getSubclassDataFromValue()+Amt);
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| /external/clang/include/clang/Analysis/Analyses/ |
| D | FormatString.h | 376 void setFieldWidth(const OptionalAmount &Amt) { in setFieldWidth() argument
377 FieldWidth = Amt; in setFieldWidth()
483 void setPrecision(const OptionalAmount &Amt) { in setPrecision() argument
484 Precision = Amt; in setPrecision()
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| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCasts.cpp | 125 Value *Amt = nullptr; in PromoteCastOfAllocation() local
127 Amt = NumElements; in PromoteCastOfAllocation()
129 Amt = ConstantInt::get(AI.getArraySize()->getType(), Scale); in PromoteCastOfAllocation()
131 Amt = AllocaBuilder.CreateMul(Amt, NumElements); in PromoteCastOfAllocation()
137 Amt = AllocaBuilder.CreateAdd(Amt, Off); in PromoteCastOfAllocation()
140 AllocaInst *New = AllocaBuilder.CreateAlloca(CastElTy, Amt); in PromoteCastOfAllocation()
781 if (ConstantInt *Amt = dyn_cast<ConstantInt>(I->getOperand(1))) { in canEvaluateZExtd() local
784 uint64_t ShiftAmt = Amt->getZExtValue(); in canEvaluateZExtd()
792 if (ConstantInt *Amt = dyn_cast<ConstantInt>(I->getOperand(1))) { in canEvaluateZExtd() local
795 BitsToClear += Amt->getZExtValue(); in canEvaluateZExtd()
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| D | InstCombineSimplifyDemanded.cpp | 849 Constant *Amt = ConstantInt::get(VarX->getType(), ShlAmt - ShrAmt); in SimplifyShrShlDemandedBits() local
850 New = BinaryOperator::CreateShl(VarX, Amt); in SimplifyShrShlDemandedBits()
855 Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt); in SimplifyShrShlDemandedBits() local
856 New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) : in SimplifyShrShlDemandedBits()
857 BinaryOperator::CreateAShr(VarX, Amt); in SimplifyShrShlDemandedBits()
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | rem.ll | 55 %Amt = shl i32 32, %shift.upgrd.1
56 %V = urem i32 %X, %Amt
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 18311 SDValue Amt = Op.getOperand(1); in LowerScalarImmediateShift() local
18349 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) { in LowerScalarImmediateShift()
18403 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); in LowerScalarImmediateShift()
18423 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode())) in LowerScalarImmediateShift()
18426 Amt = Amt.getOperand(0); in LowerScalarImmediateShift()
18431 if (Amt.getOpcode() != ISD::BITCAST || in LowerScalarImmediateShift()
18432 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR) in LowerScalarImmediateShift()
18435 Amt = Amt.getOperand(0); in LowerScalarImmediateShift()
18436 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() / in LowerScalarImmediateShift()
18442 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp)); in LowerScalarImmediateShift()
[all …]
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 715 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand() local
717 O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt) in printShiftImmOperand()
719 } else if (Amt) { in printShiftImmOperand()
720 O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">"); in printShiftImmOperand()
|
| /external/llvm/lib/IR/ |
| D | ConstantFold.cpp | 267 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); in ExtractConstantBytes() local
268 if (!Amt) in ExtractConstantBytes()
270 unsigned ShAmt = Amt->getZExtValue(); in ExtractConstantBytes()
289 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); in ExtractConstantBytes() local
290 if (!Amt) in ExtractConstantBytes()
292 unsigned ShAmt = Amt->getZExtValue(); in ExtractConstantBytes()
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| D | Instructions.cpp | 1109 static Value *getAISize(LLVMContext &Context, Value *Amt) { in getAISize() argument
1110 if (!Amt) in getAISize()
1111 Amt = ConstantInt::get(Type::getInt32Ty(Context), 1); in getAISize()
1113 assert(!isa<BasicBlock>(Amt) && in getAISize()
1115 assert(Amt->getType()->isIntegerTy() && in getAISize()
1118 return Amt; in getAISize()
|
| /external/clang/lib/Sema/ |
| D | SemaChecking.cpp | 3727 bool HandleAmount(const analyze_format_string::OptionalAmount &Amt, unsigned k,
3730 const analyze_printf::OptionalAmount &Amt,
3770 const analyze_format_string::OptionalAmount &Amt, in HandleAmount() argument
3774 if (Amt.hasDataArgument()) { in HandleAmount()
3776 unsigned argIndex = Amt.getArgIndex(); in HandleAmount()
3780 getLocationOfByte(Amt.getStart()), in HandleAmount()
3799 const analyze_printf::ArgType &AT = Amt.getArgType(S.Context); in HandleAmount()
3806 getLocationOfByte(Amt.getStart()), in HandleAmount()
3820 const analyze_printf::OptionalAmount &Amt, in HandleInvalidAmount() argument
3828 Amt.getHowSpecified() == analyze_printf::OptionalAmount::Constant in HandleInvalidAmount()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 6651 SDValue Amt = Op.getOperand(2); in LowerSHL_PARTS() local
6652 EVT AmtVT = Amt.getValueType(); in LowerSHL_PARTS()
6655 DAG.getConstant(BitWidth, dl, AmtVT), Amt); in LowerSHL_PARTS()
6656 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); in LowerSHL_PARTS()
6659 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSHL_PARTS()
6663 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); in LowerSHL_PARTS()
6680 SDValue Amt = Op.getOperand(2); in LowerSRL_PARTS() local
6681 EVT AmtVT = Amt.getValueType(); in LowerSRL_PARTS()
6684 DAG.getConstant(BitWidth, dl, AmtVT), Amt); in LowerSRL_PARTS()
6685 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRL_PARTS()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 173 unsigned Amt = ARM_AM::getAM2Offset(OffImm); in convertToThreeAddress() local
175 if (ARM_AM::getSOImmVal(Amt) == -1) in convertToThreeAddress()
181 .addReg(BaseReg).addImm(Amt) in convertToThreeAddress()
183 } else if (Amt != 0) { in convertToThreeAddress()
185 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); in convertToThreeAddress()
199 unsigned Amt = ARM_AM::getAM3Offset(OffImm); in convertToThreeAddress() local
204 .addReg(BaseReg).addImm(Amt) in convertToThreeAddress()
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