/external/llvm/test/CodeGen/X86/ |
D | TruncAssertZext.ll | 3 ; the source of the zext is an AssertSext node
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 57 AssertSext, AssertZext, enumerator
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeIntegerTypes.cpp | 53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult() 170 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext() 431 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT() 953 if (OpL->getOpcode() == ISD::AssertSext && in PromoteSetCCOperands() 955 OpR->getOpcode() == ISD::AssertSext && in PromoteSetCCOperands() 1307 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; in ExpandIntegerResult() 1848 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, in ExpandIntRes_AssertSext() 1852 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertSext()
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D | SelectionDAGDumper.cpp | 85 case ISD::AssertSext: return "AssertSext"; in getOperationName()
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D | SelectionDAGBuilder.cpp | 700 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs() 4239 case ISD::AssertSext: in getUnderlyingArgReg() 7224 AssertOp = ISD::AssertSext; in LowerCallTo() 7482 AssertOp = ISD::AssertSext; in LowerArguments()
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D | SelectionDAGISel.cpp | 2624 case ISD::AssertSext: in SelectCodeCommon()
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D | SelectionDAG.cpp | 2535 case ISD::AssertSext: in ComputeNumSignBits() 3578 case ISD::AssertSext: in getNode()
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D | DAGCombiner.cpp | 980 case ISD::AssertSext: in PromoteOperand() 981 return DAG.getNode(ISD::AssertSext, dl, PVT, in PromoteOperand()
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/external/llvm/lib/Target/BPF/ |
D | BPFISelLowering.cpp | 227 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 462 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32() 631 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64() 1353 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
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/external/llvm/lib/Target/MSP430/ |
D | MSP430ISelLowering.cpp | 471 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelDAGToDAG.cpp | 1515 case ISD::AssertSext: in isValueExtension()
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D | HexagonISelLowering.cpp | 1196 N.getOperand(0).getOpcode() == ISD::AssertSext) in isSExtFree()
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/external/llvm/include/llvm/Target/ |
D | TargetSelectionDAG.td | 571 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 2869 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult() 2919 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
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/external/llvm/lib/Target/X86/ |
D | X86InstrCompiler.td | 1211 N->getOpcode() != ISD::AssertSext &&
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D | X86ISelLowering.cpp | 2740 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 3027 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, in extendArgForPPC64() 4345 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, in LowerCallResult()
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZISelLowering.cpp | 808 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 9198 case ISD::AssertSext: { in checkValueWidth()
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 3195 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
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