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Searched refs:CTLZ (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll8 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
28 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTLZ]]
48 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTLZ]]
128 ; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
129 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTLZ]]
147 ; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
148 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTLZ]]
[all …]
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll9 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
10 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTLZ]]
28 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTLZ]]
48 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTLZ]]
177 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
178 ; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTLZ]] to i64
200 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
201 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i32
[all …]
/external/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll8 ; CHECK-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
28 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dnon-vectorizable-intrinsic.ll6 ; CTLZ cannot be vectorized currently because the second argument is a scalar
9 ; Test causes an assert if LLVM tries to vectorize CTLZ.
/external/llvm/lib/Transforms/Utils/
DIntegerDivision.cpp183 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, in generateUnsignedDivisionCode() local
255 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode()
256 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h339 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h771 ISD::CTLZ, 0),
773 ISD::CTLZ, 0),
775 ISD::CTLZ, 0),
777 ISD::CTLZ, 0),
779 ISD::CTLZ, 0),
781 ISD::CTLZ, 0),
DX86ISelLowering.cpp354 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); in X86TargetLowering()
355 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); in X86TargetLowering()
363 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); in X86TargetLowering()
364 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); in X86TargetLowering()
365 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); in X86TargetLowering()
370 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); in X86TargetLowering()
728 setOperationAction(ISD::CTLZ, VT, Expand); in X86TargetLowering()
1526 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal); in X86TargetLowering()
1527 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal); in X86TargetLowering()
1531 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom); in X86TargetLowering()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp320 case ISD::CTLZ: return "ctlz"; in getOperationName()
DLegalizeDAG.cpp2942 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op); in ExpandBitCount()
2943 case ISD::CTLZ: { in ExpandBitCount()
2979 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) in ExpandBitCount()
2982 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); in ExpandBitCount()
2995 case ISD::CTLZ: in ExpandNode()
4231 case ISD::CTLZ: in PromoteNode()
4246 } else if (Node->getOpcode() == ISD::CTLZ || in PromoteNode()
DLegalizeVectorTypes.cpp72 case ISD::CTLZ: in ScalarizeVectorResult()
627 case ISD::CTLZ: in SplitVectorResult()
1442 case ISD::CTLZ: in SplitVectorOperand()
2087 case ISD::CTLZ: in WidenVectorResult()
DLegalizeVectorOps.cpp285 case ISD::CTLZ: in LegalizeOp()
DLegalizeIntegerTypes.cpp63 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
1313 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; in ExpandIntegerResult()
DSelectionDAG.cpp2271 case ISD::CTLZ: in computeKnownBits()
2907 case ISD::CTLZ: in getNode()
2999 case ISD::CTLZ: in getNode()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp139 setOperationAction(ISD::CTLZ, MVT::i64, Custom); in BPFTargetLowering()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp122 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering()
123 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp158 setOperationAction(ISD::CTLZ, VT, Expand); in InitAMDILLowering()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1667 setOperationAction(ISD::CTLZ, MVT::i8, Promote); in HexagonTargetLowering()
1668 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in HexagonTargetLowering()
1754 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::CTLZ_ZERO_UNDEF, in HexagonTargetLowering()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp257 setOperationAction(ISD::CTLZ, MVT::i16, Legal); in NVPTXTargetLowering()
258 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in NVPTXTargetLowering()
259 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in NVPTXTargetLowering()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp227 setOperationAction(ISD::CTLZ, MVT::i32, Promote); in SystemZTargetLowering()
228 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in SystemZTargetLowering()
312 setOperationAction(ISD::CTLZ, VT, Legal); in SystemZTargetLowering()
4352 return DAG.getNode(ISD::CTLZ, SDLoc(Op), in LowerOperation()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp255 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
331 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp262 setOperationAction(ISD::CTLZ, Ty, Legal); in addMSAIntType()
2051 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
DMipsISelLowering.cpp408 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in MipsTargetLowering()
410 setOperationAction(ISD::CTLZ, MVT::i64, Expand); in MipsTargetLowering()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1578 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1633 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td402 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;

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