/external/llvm/test/Transforms/SimplifyCFG/AMDGPU/ |
D | cttz-ctlz.ll | 68 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true) 69 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]] 88 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true) 89 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTTZ]] 108 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true) 109 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTTZ]] 187 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true) 188 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTTZ]] 207 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true) 208 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTTZ]] [all …]
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/external/llvm/test/Transforms/InstCombine/ |
D | ffs-1.ll | 108 ; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true) 109 ; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1 119 ; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true) 120 ; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1 130 ; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 true) 131 ; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i64 [[CTTZ]], 1
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/external/llvm/test/Transforms/SimplifyCFG/X86/ |
D | speculate-cttz-ctlz.ll | 68 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true) 69 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTTZ]] 88 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true) 89 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTTZ]] 108 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true) 109 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTTZ]] 131 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 true) 132 ; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTTZ]] to i64 154 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 true) 155 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i32 [all …]
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/external/llvm/test/Transforms/SimplifyCFG/PowerPC/ |
D | cttz-ctlz-spec.ll | 27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 339 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 318 case ISD::CTTZ: return "cttz"; in getOperationName()
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D | LegalizeVectorTypes.cpp | 75 case ISD::CTTZ: in ScalarizeVectorResult() 628 case ISD::CTTZ: in SplitVectorResult() 1441 case ISD::CTTZ: in SplitVectorOperand() 2089 case ISD::CTTZ: in WidenVectorResult()
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D | LegalizeDAG.cpp | 2966 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op); in ExpandBitCount() 2967 case ISD::CTTZ: { in ExpandBitCount() 2997 case ISD::CTTZ: in ExpandNode() 4229 case ISD::CTTZ: in PromoteNode() 4239 if (Node->getOpcode() == ISD::CTTZ) { in PromoteNode()
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D | LegalizeVectorOps.cpp | 286 case ISD::CTTZ: in LegalizeOp()
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D | LegalizeIntegerTypes.cpp | 66 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; in PromoteIntegerResult() 393 if (N->getOpcode() == ISD::CTTZ) { in PromoteIntRes_CTTZ() 1316 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; in ExpandIntegerResult()
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D | SelectionDAG.cpp | 2269 case ISD::CTTZ: in computeKnownBits() 2911 case ISD::CTTZ: in getNode() 3001 case ISD::CTTZ: in getNode()
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D | DAGCombiner.cpp | 1393 case ISD::CTTZ: return visitCTTZ(N); in visit() 4954 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0); in visitCTTZ()
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/external/llvm/lib/Target/BPF/ |
D | BPFISelLowering.cpp | 138 setOperationAction(ISD::CTTZ, MVT::i64, Custom); in BPFTargetLowering()
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/external/llvm/lib/Target/MSP430/ |
D | MSP430ISelLowering.cpp | 118 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering() 119 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | AMDILISelLowering.cpp | 157 setOperationAction(ISD::CTTZ, VT, Expand); in InitAMDILLowering()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 1669 setOperationAction(ISD::CTTZ, MVT::i8, Promote); in HexagonTargetLowering() 1670 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in HexagonTargetLowering() 1754 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::CTLZ_ZERO_UNDEF, in HexagonTargetLowering()
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 586 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom); in ARMTargetLowering() 587 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom); in ARMTargetLowering() 588 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom); in ARMTargetLowering() 589 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in ARMTargetLowering() 591 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom); in ARMTargetLowering() 592 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom); in ARMTargetLowering() 593 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom); in ARMTargetLowering() 594 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom); in ARMTargetLowering() 756 setOperationAction(ISD::CTTZ, MVT::i32, Custom); in ARMTargetLowering() 6865 case ISD::CTTZ: in LowerOperation()
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/external/llvm/lib/Target/NVPTX/ |
D | NVPTXISelLowering.cpp | 263 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in NVPTXTargetLowering() 264 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in NVPTXTargetLowering() 265 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in NVPTXTargetLowering()
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/external/llvm/lib/Target/AMDGPU/ |
D | AMDGPUISelLowering.cpp | 254 setOperationAction(ISD::CTTZ, VT, Expand); in AMDGPUTargetLowering() 329 setOperationAction(ISD::CTTZ, VT, Expand); in AMDGPUTargetLowering()
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 335 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); in X86TargetLowering() 336 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); in X86TargetLowering() 345 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); in X86TargetLowering() 346 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); in X86TargetLowering() 348 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); in X86TargetLowering() 726 setOperationAction(ISD::CTTZ, VT, Expand); in X86TargetLowering() 867 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom); in X86TargetLowering() 868 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom); in X86TargetLowering() 869 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom); in X86TargetLowering() 1154 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom); in X86TargetLowering() [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 1576 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering() 1631 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
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/external/llvm/include/llvm/Target/ |
D | TargetSelectionDAG.td | 403 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZISelLowering.cpp | 186 setOperationAction(ISD::CTTZ, VT, Expand); in SystemZTargetLowering() 311 setOperationAction(ISD::CTTZ, VT, Legal); in SystemZTargetLowering() 4355 return DAG.getNode(ISD::CTTZ, SDLoc(Op), in LowerOperation()
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 342 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in MipsTargetLowering() 343 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in MipsTargetLowering()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 209 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); in PPCTargetLowering() 213 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); in PPCTargetLowering() 483 setOperationAction(ISD::CTTZ, VT, Expand); in PPCTargetLowering()
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