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Searched refs:DCI (Results 1 – 25 of 35) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.h51 DAGCombinerInfo &DCI) const;
54 DAGCombinerInfo &DCI) const;
55 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
56 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
57 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
59 SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
60 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
106 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
DAMDGPUISelLowering.h67 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
68 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
69 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
157 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
171 DAGCombinerInfo &DCI) const;
176 DAGCombinerInfo &DCI,
180 DAGCombinerInfo &DCI,
DSIISelLowering.cpp1622 DAGCombinerInfo &DCI) const { in performUCharToFloatCombine()
1628 SelectionDAG &DAG = DCI.DAG; in performUCharToFloatCombine()
1638 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) { in performUCharToFloatCombine()
1641 DCI.AddToWorklist(Cvt.getNode()); in performUCharToFloatCombine()
1650 if (!DCI.isBeforeLegalize() || in performUCharToFloatCombine()
1656 assert(DCI.isBeforeLegalize() && "Unexpected legal type"); in performUCharToFloatCombine()
1709 DCI.AddToWorklist(Cvt.getNode()); in performUCharToFloatCombine()
1769 DAGCombinerInfo &DCI) const { in performSHLPtrCombine()
1790 SelectionDAG &DAG = DCI.DAG; in performSHLPtrCombine()
1801 DAGCombinerInfo &DCI) const { in performAndCombine()
[all …]
DAMDGPUISelLowering.cpp1091 DAGCombinerInfo &DCI) const { in CombineFMinMaxLegacy()
1098 SelectionDAG &DAG = DCI.DAG; in CombineFMinMaxLegacy()
1128 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG && in CombineFMinMaxLegacy()
1129 !DCI.isCalledByLegalizer()) in CombineFMinMaxLegacy()
1149 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG && in CombineFMinMaxLegacy()
1150 !DCI.isCalledByLegalizer()) in CombineFMinMaxLegacy()
2316 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) { in simplifyI24() argument
2318 SelectionDAG &DAG = DCI.DAG; in simplifyI24()
2326 DCI.CommitTargetLoweringOpt(TLO); in simplifyI24()
2355 DAGCombinerInfo &DCI) const { in performStoreCombine()
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DR600ISelLowering.h30 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
DR600ISelLowering.cpp1128 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in LowerSELECT_CC() local
1129 SDValue MinMax = CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI); in LowerSELECT_CC()
1835 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
1836 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
1839 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
1956 SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
1988 if (DCI.isBeforeLegalizeOps() || in PerformDAGCombine()
2053 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h492 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
493 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
495 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
865 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
866 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
867 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
869 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
872 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
DPPCISelLowering.cpp9156 DAGCombinerInfo &DCI, in getRsqrtEstimate() argument
9166 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; in getRsqrtEstimate()
9173 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand); in getRsqrtEstimate()
9179 DAGCombinerInfo &DCI, in getRecipEstimate() argument
9188 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; in getRecipEstimate()
9194 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand); in getRecipEstimate()
9444 DAGCombinerInfo &DCI) const { in DAGCombineTruncBoolExt()
9445 SelectionDAG &DAG = DCI.DAG; in DAGCombineTruncBoolExt()
9722 DAGCombinerInfo &DCI) const { in DAGCombineExtBoolTrunc()
9723 SelectionDAG &DAG = DCI.DAG; in DAGCombineExtBoolTrunc()
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/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp1260 DAGCombinerInfo &DCI, SDLoc dl) const { in SimplifySetCC() argument
1261 SelectionDAG &DAG = DCI.DAG; in SimplifySetCC()
1282 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1341 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC()
1395 if (DCI.isBeforeLegalize() && in SimplifySetCC()
1488 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1525 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
1526 DCI.AddToWorklist(ZextOp.getNode()); in SimplifySetCC()
1546 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1636 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
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/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp8334 TargetLowering::DAGCombinerInfo &DCI, in combineSelectAndUse() argument
8336 SelectionDAG &DAG = DCI.DAG; in combineSelectAndUse()
8360 TargetLowering::DAGCombinerInfo &DCI) { in combineSelectAndUseCommutative() argument
8364 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes); in combineSelectAndUseCommutative()
8369 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes); in combineSelectAndUseCommutative()
8379 TargetLowering::DAGCombinerInfo &DCI, in AddCombineToVPADDL() argument
8384 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineToVPADDL()
8438 SelectionDAG &DAG = DCI.DAG; in AddCombineToVPADDL()
8477 TargetLowering::DAGCombinerInfo &DCI, in AddCombineTo64bitMLAL() argument
8483 if (DCI.isBeforeLegalize()) return SDValue(); in AddCombineTo64bitMLAL()
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/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.h450 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
502 unsigned Index, DAGCombinerInfo &DCI,
505 DAGCombinerInfo &DCI) const;
DSystemZISelLowering.cpp4540 DAGCombinerInfo &DCI, in combineExtract() argument
4542 SelectionDAG &DAG = DCI.DAG; in combineExtract()
4592 DCI.AddToWorklist(Op.getNode()); in combineExtract()
4597 DCI.AddToWorklist(Op.getNode()); in combineExtract()
4632 DCI.AddToWorklist(Op.getNode()); in combineExtract()
4644 DAGCombinerInfo &DCI) const { in combineTruncateExtract()
4670 return combineExtract(DL, ResVT, VecVT, Vec, NewIndex, DCI, true); in combineTruncateExtract()
4679 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
4680 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
4732 DCI.AddToWorklist(Op1.getNode()); in PerformDAGCombine()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp7367 TargetLowering::DAGCombinerInfo &DCI, in performXorCombine() argument
7369 if (DCI.isBeforeLegalizeOps()) in performXorCombine()
7418 TargetLowering::DAGCombinerInfo &DCI, in performMulCombine() argument
7420 if (DCI.isBeforeLegalizeOps()) in performMulCombine()
7715 TargetLowering::DAGCombinerInfo &DCI) { in tryCombineToEXTR() argument
7716 SelectionDAG &DAG = DCI.DAG; in tryCombineToEXTR()
7755 TargetLowering::DAGCombinerInfo &DCI) { in tryCombineToBSL() argument
7757 SelectionDAG &DAG = DCI.DAG; in tryCombineToBSL()
7801 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in performORCombine() argument
7806 SelectionDAG &DAG = DCI.DAG; in performORCombine()
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/external/mesa3d/src/gallium/drivers/radeon/
DSIISelLowering.h53 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
DSIISelLowering.cpp393 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
394 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
430 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL); in PerformDAGCombine()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp3830 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombineWithOperands() argument
3833 SelectionDAG &DAG = DCI.DAG; in PerformADDCombineWithOperands()
3936 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombine() argument
3943 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget, in PerformADDCombine()
3949 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel); in PerformADDCombine()
3953 TargetLowering::DAGCombinerInfo &DCI) { in PerformANDCombine() argument
4015 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), in PerformANDCombine()
4021 DCI.CombineTo(N, Val, AddTo); in PerformANDCombine()
4028 TargetLowering::DAGCombinerInfo &DCI) { in PerformSELECTCombine() argument
4084 return DCI.DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, in PerformSELECTCombine()
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DNVPTXISelLowering.h537 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp529 TargetLowering::DAGCombinerInfo &DCI, in performADDECombine() argument
531 if (DCI.isBeforeLegalize()) in performADDECombine()
549 TargetLowering::DAGCombinerInfo &DCI, in performANDCombine() argument
664 TargetLowering::DAGCombinerInfo &DCI, in performORCombine() argument
784 TargetLowering::DAGCombinerInfo &DCI, in performSUBECombine() argument
786 if (DCI.isBeforeLegalize()) in performSUBECombine()
835 const TargetLowering::DAGCombinerInfo &DCI, in performMULCombine() argument
874 TargetLowering::DAGCombinerInfo &DCI, in performSHLCombine() argument
897 TargetLowering::DAGCombinerInfo &DCI, in performSRACombine() argument
943 TargetLowering::DAGCombinerInfo &DCI, in performSRLCombine() argument
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DMipsSEISelLowering.h40 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
DMipsISelLowering.cpp471 TargetLowering::DAGCombinerInfo &DCI, in performDivRemCombine() argument
473 if (DCI.isBeforeLegalizeOps()) in performDivRemCombine()
581 TargetLowering::DAGCombinerInfo &DCI, in performSELECTCombine() argument
583 if (DCI.isBeforeLegalizeOps()) in performSELECTCombine()
660 TargetLowering::DAGCombinerInfo &DCI, in performCMovFPCombine() argument
662 if (DCI.isBeforeLegalizeOps()) in performCMovFPCombine()
687 TargetLowering::DAGCombinerInfo &DCI, in performANDCombine() argument
692 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performANDCombine()
729 TargetLowering::DAGCombinerInfo &DCI, in performORCombine() argument
735 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performORCombine()
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/external/llvm/lib/Target/X86/
DX86ISelLowering.h692 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
1144 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1149 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
DX86ISelLowering.cpp14056 DAGCombinerInfo &DCI, in getRsqrtEstimate() argument
14077 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; in getRsqrtEstimate()
14083 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op); in getRsqrtEstimate()
14089 DAGCombinerInfo &DCI, in getRecipEstimate() argument
14109 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; in getRecipEstimate()
14114 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op); in getRecipEstimate()
22647 TargetLowering::DAGCombinerInfo &DCI, in PerformShuffleCombine256() argument
22716 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
22727 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
22734 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
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/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1619 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
1620 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
1635 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1636 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1641 DCI.CommitTargetLoweringOpt(TLO); in PerformDAGCombine()
1652 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1653 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1658 DCI.CommitTargetLoweringOpt(TLO); in PerformDAGCombine()
1816 if (!DCI.isBeforeLegalize() || in PerformDAGCombine()
1829 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); in PerformDAGCombine()
DXCoreISelLowering.h200 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
/external/llvm/include/llvm/Target/
DTargetLowering.h2211 DAGCombinerInfo &DCI, SDLoc dl) const;
2231 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2801 virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, in getRsqrtEstimate() argument
2815 virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, in getRecipEstimate() argument

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