Searched refs:EvenReg (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 913 const unsigned EvenReg = CSRegs[i + 1]; in determineCalleeSaves() local
915 AArch64::GPR64RegClass.contains(EvenReg)) ^ in determineCalleeSaves()
917 AArch64::FPR64RegClass.contains(EvenReg)) && in determineCalleeSaves()
921 const bool EvenRegUsed = SavedRegs.test(EvenReg); in determineCalleeSaves()
928 UnspilledCSGPRs.push_back(EvenReg); in determineCalleeSaves()
931 UnspilledCSFPRs.push_back(EvenReg); in determineCalleeSaves()
941 Reg = OddRegUsed ? EvenReg : OddReg; in determineCalleeSaves()
946 DEBUG(dbgs() << ' ' << PrintReg(EvenReg, RegInfo)); in determineCalleeSaves()
948 assert(((OddReg == AArch64::LR && EvenReg == AArch64::FP) || in determineCalleeSaves()
950 RegInfo->getEncodingValue(EvenReg))) && in determineCalleeSaves()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1522 unsigned EvenReg = MI->getOperand(0).getReg(); in FixInvalidRegPairOp() local
1524 unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false); in FixInvalidRegPairOp()
1529 bool Errata602117 = EvenReg == BaseReg && in FixInvalidRegPairOp()
1564 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1571 .addReg(EvenReg, in FixInvalidRegPairOp()
1592 (TRI->regsOverlap(EvenReg, BaseReg))) { in FixInvalidRegPairOp()
1599 EvenReg, EvenDeadKill, false, in FixInvalidRegPairOp()
1603 if (OddReg == EvenReg && EvenDeadKill) { in FixInvalidRegPairOp()
1611 if (EvenReg == BaseReg) in FixInvalidRegPairOp()
1614 EvenReg, EvenDeadKill, EvenUndef, in FixInvalidRegPairOp()
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