| /external/v8/test/unittests/interpreter/ |
| D | interpreter-assembler-unittest.cc | 77 Matcher<Node*> InterpreterAssemblerTest::InterpreterAssemblerForTest::IsLoad( in IsLoad() function in v8::internal::interpreter::InterpreterAssemblerTest::InterpreterAssemblerForTest
80 return ::i::compiler::IsLoad(rep_matcher, base_matcher, index_matcher, _, _); in IsLoad()
94 return IsLoad( in IsUnsignedByteOperand()
105 Matcher<Node*> load_matcher = IsLoad( in IsSignedByteOperand()
121 return IsLoad( in IsUnsignedShortOperand()
140 bytes[i] = IsLoad( in IsUnsignedShortOperand()
158 load_matcher = IsLoad( in IsSignedShortOperand()
177 bytes[i] = IsLoad( in IsSignedShortOperand()
199 return IsLoad( in IsUnsignedQuadOperand()
218 bytes[i] = IsLoad( in IsUnsignedQuadOperand()
[all …]
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| D | interpreter-assembler-unittest.h | 33 Matcher<compiler::Node*> IsLoad(
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| /external/llvm/lib/CodeGen/ |
| D | AtomicExpandPass.cpp | 51 bool IsStore, bool IsLoad);
103 bool IsStore, IsLoad; in runOnFunction() local
109 IsLoad = true; in runOnFunction()
114 IsLoad = false; in runOnFunction()
119 IsStore = IsLoad = true; in runOnFunction()
130 IsStore = IsLoad = true; in runOnFunction()
134 MadeChange |= bracketInstWithFences(I, FenceOrdering, IsStore, IsLoad); in runOnFunction()
179 bool IsStore, bool IsLoad) { in bracketInstWithFences() argument
182 auto LeadingFence = TLI->emitLeadingFence(Builder, Order, IsStore, IsLoad); in bracketInstWithFences()
184 auto TrailingFence = TLI->emitTrailingFence(Builder, Order, IsStore, IsLoad); in bracketInstWithFences()
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| D | InlineSpiller.cpp | 1018 bool IsLoad = InstrReg; in coalesceStackAccess() local
1019 if (!IsLoad) in coalesceStackAccess()
1030 if (IsLoad) { in coalesceStackAccess()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 78 unsigned int IsLoad : 1; member
342 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
348 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
357 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
663 else if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
674 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad || in recordUnoptimizableWebs()
697 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
728 if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
938 if (SwapVector[EntryIdx].IsLoad) in dumpSwapVector()
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| D | PPCISelLowering.h | 512 bool IsStore, bool IsLoad) const override;
514 bool IsStore, bool IsLoad) const override;
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrFormats.td | 36 bit IsLoad = 0;
52 let TSFlags{5-5} = IsLoad;
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| /external/v8/test/unittests/compiler/ |
| D | int64-lowering-unittest.cc | 138 IsLoad(MachineType::Int32(), IsInt32Constant(base), in TEST_F()
144 IsReturn2(IsLoad(MachineType::Int32(), IsInt32Constant(base), in TEST_F()
152 IsLoad(MachineType::Int32(), IsInt32Constant(base), in TEST_F()
158 IsLoad(MachineType::Int32(), IsInt32Constant(base), in TEST_F()
571 IsReturn(IsLoad(MachineType::Float64(), in TEST_F()
596 IsReturn2(IsLoad(MachineType::Int32(), in TEST_F()
600 IsLoad(MachineType::Int32(), in TEST_F()
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| /external/llvm/lib/Target/X86/Utils/ |
| D | X86ShuffleDecode.h | 109 void DecodeScalarMoveMask(MVT VT, bool IsLoad,
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| D | X86ShuffleDecode.cpp | 455 void DecodeScalarMoveMask(MVT VT, bool IsLoad, SmallVectorImpl<int> &Mask) { in DecodeScalarMoveMask() argument
461 Mask.push_back(IsLoad ? static_cast<int>(SM_SentinelZero) : i); in DecodeScalarMoveMask()
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| /external/clang/lib/StaticAnalyzer/Core/ |
| D | CheckerManager.cpp | 293 bool IsLoad; member
305 : Checkers(checkers), Loc(loc), IsLoad(isLoad), NodeEx(NodeEx), in CheckLocationContext()
310 ProgramPoint::Kind K = IsLoad ? ProgramPoint::PreLoadKind : in runChecker()
317 checkFn(Loc, IsLoad, BoundEx, C); in runChecker()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 215 bool IsLoad = TII->get(LoadStoreOp).mayLoad(); in buildScratchLoadStore() local
244 .addReg(SubReg, getDefRegState(IsLoad)) in buildScratchLoadStore()
251 .addReg(Value, RegState::Implicit | getDefRegState(IsLoad)) in buildScratchLoadStore()
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| /external/clang/lib/StaticAnalyzer/Checkers/ |
| D | CheckerDocumentation.cpp | 138 void checkLocation(SVal Loc, bool IsLoad, const Stmt *S, in checkLocation() argument
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| D | NSErrorChecker.cpp | 241 if (event.IsLoad) in checkEvent()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 454 bool IsLoad = in UpdateBaseRegUses() local
459 if (IsLoad || IsStore) { in UpdateBaseRegUses()
777 bool IsLoad = isi32Load(Opcode); in CreateLoadStoreDouble() local
778 assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store"); in CreateLoadStoreDouble()
779 unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8; in CreateLoadStoreDouble()
784 if (IsLoad) { in CreateLoadStoreDouble()
799 bool IsLoad = isLoadSingle(Opcode); in MergeOpsUpdate() local
814 if (IsLoad) { in MergeOpsUpdate()
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| D | ARMISelLowering.h | 443 bool IsStore, bool IsLoad) const override;
445 bool IsStore, bool IsLoad) const override;
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| D | ARMExpandPseudoInsts.cpp | 107 bool IsLoad; member
382 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); in ExpandVLD()
447 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); in ExpandVST()
523 if (TableEntry->IsLoad) { in ExpandLaneOp()
548 if (!TableEntry->IsLoad) in ExpandLaneOp()
573 if (TableEntry->IsLoad) in ExpandLaneOp()
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| /external/clang/lib/CodeGen/ |
| D | CGAtomic.cpp | 1035 bool IsLoad = E->getOp() == AtomicExpr::AO__c11_atomic_load || in EmitAtomicExpr() local
1054 if (IsLoad) in EmitAtomicExpr()
1060 if (IsLoad || IsStore) in EmitAtomicExpr()
1091 if (!IsLoad) in EmitAtomicExpr()
1093 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1120 if (!IsLoad) { in EmitAtomicExpr()
1128 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
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| /external/v8/src/arm64/ |
| D | instructions-arm64.cc | 16 bool Instruction::IsLoad() const { in IsLoad() function in v8::internal::Instruction
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| D | instructions-arm64.h | 230 bool IsLoad() const;
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| /external/vixl/src/vixl/a64/ |
| D | instructions-a64.cc | 74 bool Instruction::IsLoad() const { in IsLoad() function in vixl::Instruction
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| D | instructions-a64.h | 269 bool IsLoad() const;
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1070 bool IsLoad = fieldFromInstruction(insn, 22, 1); in DecodeSignedLdStInstruction() local
1075 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) in DecodeSignedLdStInstruction()
1171 bool IsLoad = fieldFromInstruction(insn, 22, 1); in DecodePairLdStInstruction() local
1282 if (IsLoad && Rt == Rt2) in DecodePairLdStInstruction()
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| /external/clang/include/clang/StaticAnalyzer/Core/ |
| D | Checker.h | 529 bool IsLoad; member
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 853 bool IsLoad = TheI->mayLoad(), IsStore = TheI->mayStore(); in canMoveMemTo() local
854 if (!IsLoad && !IsStore) in canMoveMemTo()
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