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Searched refs:MIB (Results 1 – 25 of 72) sorted by relevance

123

/external/llvm/lib/Target/X86/
DX86InstrBuilder.h91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
99 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
108 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
115 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
123 addFullAddress(const MachineInstrBuilder &MIB, in addFullAddress() argument
128 MIB.addReg(AM.Base.Reg); in addFullAddress()
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DX86ExpandPseudo.cpp99 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); in ExpandMI() local
101 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), in ExpandMI()
105 MIB.addExternalSymbol(JumpTarget.getSymbolName(), in ExpandMI()
112 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); in ExpandMI() local
114 MIB.addOperand(MBBI->getOperand(i)); in ExpandMI()
DX86InstrInfo.cpp2648 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), in convertToThreeAddressWithLEA() local
2654 MIB.addReg(0).addImm(1 << ShAmt) in convertToThreeAddressWithLEA()
2659 addRegOffset(MIB, leaInReg, true, 1); in convertToThreeAddressWithLEA()
2662 addRegOffset(MIB, leaInReg, true, -1); in convertToThreeAddressWithLEA()
2668 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); in convertToThreeAddressWithLEA()
2679 addRegReg(MIB, leaInReg, true, leaInReg, false); in convertToThreeAddressWithLEA()
2687 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); in convertToThreeAddressWithLEA()
2689 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) in convertToThreeAddressWithLEA()
2692 addRegReg(MIB, leaInReg, true, leaInReg2, true); in convertToThreeAddressWithLEA()
2700 MachineInstr *NewMI = MIB; in convertToThreeAddressWithLEA()
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/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp207 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
240 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
253 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
265 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
311 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
324 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
356 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
358 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
359 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
366 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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DInstrEmitter.h52 MachineInstrBuilder &MIB,
65 void AddRegisterOperand(MachineInstrBuilder &MIB,
76 void AddOperand(MachineInstrBuilder &MIB,
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp386 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
394 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
396 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
398 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
400 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
403 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
406 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
407 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
410 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
420 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
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DARMBaseInstrInfo.cpp667 MachineInstrBuilder MIB = in copyFromCPSR() local
673 MIB.addImm(0x800); in copyFromCPSR()
675 AddDefaultPred(MIB); in copyFromCPSR()
677 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
688 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); in copyToCPSR() local
691 MIB.addImm(0x800); in copyToCPSR()
693 MIB.addImm(8); in copyToCPSR()
695 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyToCPSR()
697 AddDefaultPred(MIB); in copyToCPSR()
699 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
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DThumbRegisterInfo.cpp165 MachineInstrBuilder MIB = in emitThumbRegPlusImmInReg() local
168 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmInReg()
170 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
172 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
173 AddDefaultPred(MIB); in emitThumbRegPlusImmInReg()
306 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg); in emitThumbRegPlusImmediate() local
308 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmediate()
309 MIB.addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmediate()
311 MIB.addImm(CopyImm); in emitThumbRegPlusImmediate()
313 AddDefaultPred(MIB.setMIFlags(MIFlags)); in emitThumbRegPlusImmediate()
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DARMInstrInfo.cpp122 MachineInstrBuilder MIB; in expandLoadStackGuard() local
124 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg) in expandLoadStackGuard()
129 MIB.addMemOperand(MMO); in expandLoadStackGuard()
130 MIB = BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg); in expandLoadStackGuard()
131 MIB.addReg(Reg, RegState::Kill).addImm(0); in expandLoadStackGuard()
132 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandLoadStackGuard()
133 AddDefaultPred(MIB); in expandLoadStackGuard()
DThumb2SizeReduction.cpp505 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); in ReduceLoadStore() local
510 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead); in ReduceLoadStore()
513 MIB.addOperand(MI->getOperand(0)); in ReduceLoadStore()
514 MIB.addOperand(MI->getOperand(1)); in ReduceLoadStore()
517 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
522 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
528 MIB.addOperand(MI->getOperand(OpNum)); in ReduceLoadStore()
531 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in ReduceLoadStore()
534 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore()
536 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); in ReduceLoadStore()
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DARMFastISel.cpp215 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
217 const MachineInstrBuilder &MIB,
263 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { in AddOptionalDefs() argument
264 MachineInstr *MI = &*MIB; in AddOptionalDefs()
270 AddDefaultPred(MIB); in AddOptionalDefs()
277 AddDefaultT1CC(MIB); in AddOptionalDefs()
279 AddDefaultCC(MIB); in AddOptionalDefs()
281 return MIB; in AddOptionalDefs()
634 MachineInstrBuilder MIB; in ARMMaterializeGV() local
637 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), in ARMMaterializeGV()
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DThumb1FrameLowering.cpp454 MachineInstrBuilder MIB = in emitPopSpecialFixUp() local
460 MIB.addOperand(MO); in emitPopSpecialFixUp()
461 MIB.addReg(ARM::PC, RegState::Define); in emitPopSpecialFixUp()
536 MachineInstrBuilder MIB = in emitPopSpecialFixUp() local
543 MIB.addOperand(MO); in emitPopSpecialFixUp()
549 MBB.erase(MIB.getInstr()); in emitPopSpecialFixUp()
584 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); in spillCalleeSavedRegisters() local
585 AddDefaultPred(MIB); in spillCalleeSavedRegisters()
603 MIB.addReg(Reg, getKillRegState(isKill)); in spillCalleeSavedRegisters()
605 MIB.setMIFlags(MachineInstr::FrameSetup); in spillCalleeSavedRegisters()
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DThumb2InstrInfo.cpp154 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot() local
155 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
156 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
157 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO); in storeRegToStackSlot()
158 AddDefaultPred(MIB); in storeRegToStackSlot()
193 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); in loadRegFromStackSlot() local
194 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
195 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
196 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
197 AddDefaultPred(MIB); in loadRegFromStackSlot()
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DARMBaseInstrInfo.h203 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
395 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { in AddDefaultPred() argument
396 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); in AddDefaultPred()
400 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { in AddDefaultCC() argument
401 return MIB.addReg(0); in AddDefaultCC()
405 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
407 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
411 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { in AddNoT1CC() argument
412 return MIB.addReg(0); in AddNoT1CC()
DMLxExpansionPass.cpp293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction() local
297 MIB.addImm(LaneImm); in ExpandFPMLxInstruction()
298 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
300 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2) in ExpandFPMLxInstruction()
305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
310 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
DARMLoadStoreOptimizer.cpp738 MachineInstrBuilder MIB; in CreateLoadStoreMulti() local
748 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode)); in CreateLoadStoreMulti()
751 MIB.addReg(Base, getDefRegState(true)) in CreateLoadStoreMulti()
761 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode)); in CreateLoadStoreMulti()
762 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
765 MIB.addImm(Pred).addReg(PredReg); in CreateLoadStoreMulti()
768 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
770 return MIB.getInstr(); in CreateLoadStoreMulti()
782 MachineInstrBuilder MIB = BuildMI(MBB, InsertBefore, DL, in CreateLoadStoreDouble() local
785 MIB.addReg(Regs[0].first, RegState::Define) in CreateLoadStoreDouble()
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/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp102 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); in BuildCondBr() local
106 MIB.addReg(Cond[i].getReg()); in BuildCondBr()
108 MIB.addImm(Cond[i].getImm()); in BuildCondBr()
112 MIB.addMBB(TBB); in BuildCondBr()
280 MachineInstrBuilder MIB; in genInstrWithNewOpc() local
281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
284 MIB.addOperand(I->getOperand(J)); in genInstrWithNewOpc()
286 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end()); in genInstrWithNewOpc()
287 return MIB; in genInstrWithNewOpc()
DMips16InstrInfo.cpp84 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg() local
87 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
90 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
171 static void addSaveRestoreRegs(MachineInstrBuilder &MIB, in addSaveRestoreRegs() argument
185 MIB.addReg(Reg, Flags); in addSaveRestoreRegs()
204 MachineInstrBuilder MIB; in makeFrame() local
206 MIB = BuildMI(MBB, I, DL, get(Opc)); in makeFrame()
208 addSaveRestoreRegs(MIB, CSI); in makeFrame()
210 MIB.addReg(Mips::S2); in makeFrame()
212 MIB.addImm(FrameSize); in makeFrame()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrBuilder.h33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
/external/llvm/lib/Target/SystemZ/
DSystemZFrameLowering.cpp112 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, in addSavedGPR() argument
119 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive)); in addSavedGPR()
178 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG)); in spillCalleeSavedRegisters() local
181 addSavedGPR(MBB, MIB, LowGPR, false); in spillCalleeSavedRegisters()
182 addSavedGPR(MBB, MIB, HighGPR, false); in spillCalleeSavedRegisters()
185 MIB.addReg(SystemZ::R15D).addImm(StartOffset); in spillCalleeSavedRegisters()
192 addSavedGPR(MBB, MIB, Reg, true); in spillCalleeSavedRegisters()
198 addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true); in spillCalleeSavedRegisters()
248 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG)); in restoreCalleeSavedRegisters() local
251 MIB.addReg(LowGPR, RegState::Define); in restoreCalleeSavedRegisters()
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DSystemZInstrBuilder.h27 addFrameReference(const MachineInstrBuilder &MIB, int FI) { in addFrameReference() argument
28 MachineInstr *MI = MIB; in addFrameReference()
41 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO); in addFrameReference()
/external/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp109 MachineInstrBuilder MIB = in tryOrrMovk() local
126 transferImpOps(MI, MIB, MIB1); in tryOrrMovk()
176 MachineInstrBuilder MIB = in tryToreplicateChunks() local
207 transferImpOps(MI, MIB, MIB1); in tryToreplicateChunks()
228 transferImpOps(MI, MIB, MIB2); in tryToreplicateChunks()
359 MachineInstrBuilder MIB = in trySequenceOfOnes() local
381 transferImpOps(MI, MIB, MIB1); in trySequenceOfOnes()
395 transferImpOps(MI, MIB, MIB2); in trySequenceOfOnes()
414 MachineInstrBuilder MIB = in expandMOVImm() local
419 transferImpOps(MI, MIB, MIB); in expandMOVImm()
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/external/llvm/lib/Target/Hexagon/
DHexagonFixupHwLoops.cpp166 MachineInstrBuilder MIB; in useExtLoopInstr() local
184 MIB = BuildMI(*MBB, MII, DL, TII->get(newOp)); in useExtLoopInstr()
187 MIB.addOperand(MII->getOperand(i)); in useExtLoopInstr()
/external/llvm/lib/CodeGen/
DImplicitNullChecks.cpp366 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_LOAD_OP), DefReg) in insertFaultingLoad() local
371 MIB.addOperand(MO); in insertFaultingLoad()
373 MIB.setMemRefs(LoadMI->memoperands_begin(), LoadMI->memoperands_end()); in insertFaultingLoad()
375 return MIB; in insertFaultingLoad()
DMachineInstrBundle.cpp122 MachineInstrBuilder MIB = in finalizeBundle() local
124 Bundle.prepend(MIB); in finalizeBundle()
203 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
212 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()

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