| /external/llvm/test/Analysis/BlockFrequencyInfo/ |
| D | double_exit.ll | 15 ; Pseudo-edges = exit
16 ; Pseudo-mass = 1
28 ; Pseudo-edges = outer.inc @ 1/5, exit @ 1/5
29 ; Pseudo-mass = 2/3
88 ; Pseudo-edges = exit
89 ; Pseudo-mass = 1
101 ; Pseudo-edges = outer.inc
102 ; Pseudo-mass = 1/2
114 ; Pseudo-edges = middle.inc @ 1/5, outer.inc @ 1/5
115 ; Pseudo-mass = 2/3
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrCompiler.td | 30 // Random Pseudo Instructions.
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
94 def VAARG_64 : I<0, Pseudo,
111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
121 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
[all …]
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| D | X86InstrTSX.td | 22 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
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| /external/bison/m4/ |
| D | isnanl.m4 | 200 /* The isnanl function should recognize Pseudo-NaNs, Pseudo-Infinities,
201 Pseudo-Zeroes, Unnormalized Numbers, and Pseudo-Denormals, as defined in
207 { /* Pseudo-NaN. */
213 { /* Pseudo-Infinity. */
219 { /* Pseudo-Zero. */
231 { /* Pseudo-Denormal. */
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| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 102 // Pseudo valuetype mapped to the current pointer size to any address space.
106 // Pseudo valuetype to represent "vector of any size"
109 // Pseudo valuetype to represent "float of any format"
112 // Pseudo valuetype to represent "integer of any bit width"
115 // Pseudo valuetype mapped to the current pointer size.
118 // Pseudo valuetype to represent "any type of any size".
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| /external/llvm/lib/Target/BPF/ |
| D | BPFInstrFormats.td | 28 // Pseudo instructions
29 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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| D | BPFInstrInfo.td | 236 class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
249 let Inst{55-52} = Pseudo;
440 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
443 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
449 def Select : Pseudo<(outs GPR:$dst),
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 107 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
209 def ATOMIC_LOAD_ADD_I64 : Pseudo<
212 def ATOMIC_LOAD_SUB_I64 : Pseudo<
215 def ATOMIC_LOAD_OR_I64 : Pseudo<
218 def ATOMIC_LOAD_XOR_I64 : Pseudo<
221 def ATOMIC_LOAD_AND_I64 : Pseudo<
224 def ATOMIC_LOAD_NAND_I64 : Pseudo<
228 def ATOMIC_CMP_SWAP_I64 : Pseudo<
232 def ATOMIC_SWAP_I64 : Pseudo<
255 def TCRETURNdi8 :Pseudo< (outs),
[all …]
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| D | PPCInstrInfo.td | 1016 // Pseudo-instructions:
1020 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1022 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt…
1026 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1031 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1034 def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1044 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1048 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1052 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1055 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
[all …]
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsBaseInfo.h | 105 Pseudo = 0, enumerator
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 100 Pseudo, enumerator
208 bool isPseudo() const { return Flags & (1 << MCID::Pseudo); } in isPseudo()
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| /external/squashfs-tools/RELEASE-READMEs/ |
| D | README-4.1 | 147 Pseudo operations
153 Pseudo definition
210 Pseudo definition
234 Pseudo definition
251 Pseudo definition
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| D | pseudo-file.example | 1 # Pseudo file example
21 # Pseudo file examples
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| D | README-4.0 | 27 Pseudo device nodes are specified using 7 arguments
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 328 // Pseudo-registers representing odd-even pairs of D registers. The even-odd
346 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
357 // Pseudo-registers representing 3 consecutive D registers.
368 // Pseudo 256-bit registers to represent pairs of Q registers. These should
373 // Pseudo 256-bit vector register class to model pairs of Q registers
392 // Pseudo 512-bit registers to represent four consecutive Q registers.
396 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
405 // Pseudo-registers representing 2-spaced consecutive D registers.
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| D | ARMScheduleSwift.td | 160 // Pseudo instructions.
885 (instregex "VLD2(d|q|b)(8|16|32)$", "VLD2q(8|16|32)Pseudo$")>;
921 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
928 "VLD2LN(d|q)(8|16|32)Pseudo$")>;
942 "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
953 "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
985 (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$")>;
1003 (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$")>;
1008 (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$")>;
1014 (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$")>;
[all …]
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| /external/chromium-trace/catapult/third_party/webapp2/docs/_themes/webapp2/ |
| D | pygapp2.py | 17 Keyword.Pseudo: "nobold noitalic #008",
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.h | 32 Pseudo = (1<<0), enumerator
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| D | SparcInstrInfo.td | 343 // Pseudo instructions.
344 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
352 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
356 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
359 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
381 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
385 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
390 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
395 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
403 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
[all …]
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILInstrInfo.td | 185 "; i32 Pseudo branch instruction",
189 "; f32 Pseudo branch instruction",
222 "; Pseudo unconditional branch instruction",
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFormats.td | 31 def Pseudo : Format<0>;
116 // Mips Pseudo Instructions Format
119 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
124 // Mips32/64 Pseudo Instruction Format
131 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
135 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl {
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 116 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
119 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
125 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
129 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
134 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
137 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
140 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
143 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
146 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
149 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
[all …]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFP.td | 61 def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>;
62 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>;
63 def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>;
125 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
141 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 228 Pseudo = 0, enumerator
667 case X86II::Pseudo: in getMemoryOperandNo()
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| /external/llvm/lib/Target/Hexagon/ |
| D | Hexagon.td | 218 let KeyCol = ["Pseudo"];
219 let ValueCols = [["Pseudo"], ["Real"]];
|