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Searched refs:R31 (Results 1 – 23 of 23) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonIsetDx.td32 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBr…
42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAc…
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
122 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBran…
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
221 let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = Double…
277 let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffect…
536 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPr…
560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWo…
599 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBra…
[all …]
DHexagonRegisterInfo.cpp43 : HexagonGenRegisterInfo(Hexagon::R31) {} in HexagonRegisterInfo()
104 Reserved.set(Hexagon::R31); in getReservedRegs()
168 return Hexagon::R31; in getRARegister()
DHexagonRegisterInfo.td93 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
112 def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>;
206 R10, R11, R29, R30, R31)> {
261 R28, R31,
DHexagonInstrInfo.cpp3260 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)) in getDuplexCandidateGroup()
3274 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))) in getDuplexCandidateGroup()
DHexagonInstrInfo.td1595 (JMPret (i32 R31))>;
1605 (EH_RETURN_JMPR (i32 R31))>;
2014 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in
3656 let Defs = [R29, R30], Uses = [R29, R31, R30],
4890 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
4895 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
DHexagonInstrInfoV4.td3277 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in
3282 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
3289 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
3296 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
/external/valgrind/VEX/orig_ppc32/
Ddate.orig139 70: GETL R31, t52
347 1: PUTL t0, R31
864 8: PUTL t6, R31
868 10: GETL R31, t8
1146 63: GETL R31, t50
1203 24: PUTL t18, R31
1288 9: GETL R31, t8
1351 50: GETL R31, t32
1357 54: GETL R31, t36
1364 59: GETL R31, t40
[all …]
Dreturn0.orig139 70: GETL R31, t52
347 1: PUTL t0, R31
864 8: PUTL t6, R31
868 10: GETL R31, t8
1146 63: GETL R31, t50
1203 24: PUTL t18, R31
1288 9: GETL R31, t8
1351 50: GETL R31, t32
1357 54: GETL R31, t36
1364 59: GETL R31, t40
[all …]
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td76 def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
90 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
121 R30, R31, R26, R27,
139 R30, R31, R26, R27,
/external/libgdx/extensions/gdx-bullet/jni/src/bullet/BulletCollision/CollisionDispatch/
DbtBoxBoxDetector.cpp271 btScalar A[3],B[3],R11,R12,R13,R21,R22,R23,R31,R32,R33, in dBoxBox2() local
290 R31 = dDOT44(R1+2,R2+0); R32 = dDOT44(R1+2,R2+1); R33 = dDOT44(R1+2,R2+2); in dBoxBox2()
294 Q31 = btFabs(R31); Q32 = btFabs(R32); Q33 = btFabs(R33); in dBoxBox2()
363 TST(pp[2]*R21-pp[1]*R31,(A[1]*Q31+A[2]*Q21+B[1]*Q13+B[2]*Q12),0,-R31,R21,7); in dBoxBox2()
368 TST(pp[0]*R31-pp[2]*R11,(A[0]*Q31+A[2]*Q11+B[1]*Q23+B[2]*Q22),R31,0,-R11,10); in dBoxBox2()
/external/autotest/site_utils/autoupdate/
Drelease_config.ini15 R23, R24, R25, R26, R27, R28, R29, R30, R31
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp272 if (Hexagon::R31 == DstReg) { in getDuplexCandidateGroup()
291 (Hexagon::R31 == DstReg)) { in getDuplexCandidateGroup()
627 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
630 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
DHexagonMCChecker.cpp92 if (Hexagon::R31 != R && MCID.isCall()) in init()
DHexagonMCInstrInfo.cpp465 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31); in isIntReg()
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp102 static const SpillSlot darwinOffsets = {PPC::R31, -4}; in getCalleeSavedSpillSlots()
138 {PPC::R31, -4}, in getCalleeSavedSpillSlots()
522 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; in replaceFPWithRealFP()
673 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; in emitPrologue()
1014 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; in emitEpilogue()
1307 unsigned MinGPR = PPC::R31; in processFunctionBeforeFrameFinalized()
DPPCCallingConv.td214 R29, R30, R31, F14, F15, F16, F17, F18,
223 R29, R30, R31, F14, F15, F16, F17, F18,
DPPCRegisterInfo.cpp233 Reserved.set(PPC::R31); in getReservedRegs()
360 .addReg(PPC::R31) in lowerDynamicAlloc()
897 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; in getFrameRegister()
DPPCRegisterInfo.td235 R31, R0, R1, FP, BP)> {
DPPCISelLowering.cpp8505 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; in emitEHSjLjLongJmp()
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp171 PPC::R28, PPC::R29, PPC::R30, PPC::R31
182 PPC::R28, PPC::R29, PPC::R30, PPC::R31
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp44 PPC::R28, PPC::R29, PPC::R30, PPC::R31
55 PPC::R28, PPC::R29, PPC::R30, PPC::R31
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp499 Hexagon::R30, Hexagon::R31}; in DecodeIntRegsRegisterClass()
/external/llvm/docs/
DLangRef.rst3413 ``R1-R31``).