1//===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the Hexagon register file. 12//===----------------------------------------------------------------------===// 13 14let Namespace = "Hexagon" in { 15 16 class HexagonReg<bits<5> num, string n, list<string> alt = [], 17 list<Register> alias = []> : Register<n> { 18 field bits<5> Num; 19 let Aliases = alias; 20 let HWEncoding{4-0} = num; 21 } 22 23 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs, 24 list<string> alt = []> : 25 RegisterWithSubRegs<n, subregs> { 26 field bits<5> Num; 27 28 let AltNames = alt; 29 let HWEncoding{4-0} = num; 30 } 31 32 // Registers are identified with 5-bit ID numbers. 33 // Ri - 32-bit integer registers. 34 class Ri<bits<5> num, string n, list<string> alt = []> : HexagonReg<num, n, alt> { 35 let Num = num; 36 } 37 38 // Rf - 32-bit floating-point registers. 39 class Rf<bits<5> num, string n> : HexagonReg<num, n> { 40 let Num = num; 41 } 42 43 44 // Rd - 64-bit registers. 45 class Rd<bits<5> num, string n, list<Register> subregs> : 46 HexagonDoubleReg<num, n, subregs> { 47 let Num = num; 48 let SubRegs = subregs; 49 } 50 51 // Rp - predicate registers 52 class Rp<bits<5> num, string n> : HexagonReg<num, n> { 53 let Num = num; 54 } 55 56 57 // Rq - vector predicate registers 58 class Rq<bits<3> num, string n> : Register<n, []> { 59 let HWEncoding{2-0} = num; 60 } 61 62 // Rc - control registers 63 class Rc<bits<5> num, string n, 64 list<string> alt = [], list<Register> alias = []> : 65 HexagonReg<num, n, alt, alias> { 66 let Num = num; 67 } 68 69 // Rcc - 64-bit control registers. 70 class Rcc<bits<5> num, string n, list<Register> subregs, 71 list<string> alt = []> : 72 HexagonDoubleReg<num, n, subregs, alt> { 73 let Num = num; 74 let SubRegs = subregs; 75 } 76 77 // Mx - address modifier registers 78 class Mx<bits<1> num, string n> : HexagonReg<{0b0000, num}, n> { 79 let Num = !cast<bits<5>>(num); 80 } 81 82 def subreg_loreg : SubRegIndex<32>; 83 def subreg_hireg : SubRegIndex<32, 32>; 84 def subreg_overflow : SubRegIndex<1, 0>; 85 86 // Integer registers. 87 foreach i = 0-28 in { 88 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>; 89 } 90 91 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>; 92 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>; 93 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>; 94 95 // Aliases of the R* registers used to hold 64-bit int values (doubles). 96 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { 97 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; 98 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; 99 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; 100 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; 101 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; 102 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>; 103 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>; 104 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>; 105 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>; 106 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>; 107 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>; 108 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>; 109 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>; 110 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>; 111 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>; 112 def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>; 113 } 114 115 // Predicate registers. 116 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>; 117 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>; 118 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>; 119 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>; 120 121 // Modifier registers. 122 // C6 and C7 can also be M0 and M1, but register names must be unique, even 123 // if belonging to different register classes. 124 def M0 : Mx<0, "m0">, DwarfRegNum<[72]>; 125 def M1 : Mx<1, "m1">, DwarfRegNum<[73]>; 126 127 // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc- 128 // tions modify this bit, and multiple such instructions are allowed in the 129 // same packet. We need to ignore output dependencies on this bit, but not 130 // on the entire USR. 131 def USR_OVF : Rc<?, "usr.ovf">; 132 133 // Control registers. 134 def SA0 : Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>; 135 def LC0 : Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>; 136 def SA1 : Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>; 137 def LC1 : Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>; 138 def P3_0 : Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>, 139 DwarfRegNum<[71]>; 140 def C5 : Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; // future use 141 def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[73]>; 142 def C7 : Rc<7, "c7", [], [M1]>, DwarfRegNum<[74]>; 143 144 def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[75]> { 145 let SubRegIndices = [subreg_overflow]; 146 let SubRegs = [USR_OVF]; 147 } 148 def PC : Rc<9, "pc">, DwarfRegNum<[76]>; 149 def UGP : Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>; 150 def GP : Rc<11, "gp">, DwarfRegNum<[78]>; 151 def CS0 : Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>; 152 def CS1 : Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>; 153 def UPCL : Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>; 154 def UPCH : Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>; 155} 156 157 // Control registers pairs. 158 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { 159 def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; 160 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; 161 def C7_6 : Rcc<6, "c7:6", [C6, C7], ["m1:0"]>, DwarfRegNum<[72]>; 162 def C9_8 : Rcc<8, "c9:8", [USR, PC]>, DwarfRegNum<[74]>; 163 def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; 164 def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; 165 def UPC : Rcc<14, "c15:14", [UPCL, UPCH]>, DwarfRegNum<[80]>; 166 } 167 168 foreach i = 0-31 in { 169 def V#i : Ri<i, "v"#i>, DwarfRegNum<[!add(i, 99)]>; 170 } 171 172 // Aliases of the V* registers used to hold double vec values. 173 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { 174 def W0 : Rd< 0, "v1:0", [V0, V1]>, DwarfRegNum<[99]>; 175 def W1 : Rd< 2, "v3:2", [V2, V3]>, DwarfRegNum<[101]>; 176 def W2 : Rd< 4, "v5:4", [V4, V5]>, DwarfRegNum<[103]>; 177 def W3 : Rd< 6, "v7:6", [V6, V7]>, DwarfRegNum<[105]>; 178 def W4 : Rd< 8, "v9:8", [V8, V9]>, DwarfRegNum<[107]>; 179 def W5 : Rd<10, "v11:10", [V10, V11]>, DwarfRegNum<[109]>; 180 def W6 : Rd<12, "v13:12", [V12, V13]>, DwarfRegNum<[111]>; 181 def W7 : Rd<14, "v15:14", [V14, V15]>, DwarfRegNum<[113]>; 182 def W8 : Rd<16, "v17:16", [V16, V17]>, DwarfRegNum<[115]>; 183 def W9 : Rd<18, "v19:18", [V18, V19]>, DwarfRegNum<[117]>; 184 def W10 : Rd<20, "v21:20", [V20, V21]>, DwarfRegNum<[119]>; 185 def W11 : Rd<22, "v23:22", [V22, V23]>, DwarfRegNum<[121]>; 186 def W12 : Rd<24, "v25:24", [V24, V25]>, DwarfRegNum<[123]>; 187 def W13 : Rd<26, "v27:26", [V26, V27]>, DwarfRegNum<[125]>; 188 def W14 : Rd<28, "v29:28", [V28, V29]>, DwarfRegNum<[127]>; 189 def W15 : Rd<30, "v31:30", [V30, V31]>, DwarfRegNum<[129]>; 190 } 191 192 // Vector Predicate registers. 193 def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>; 194 def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>; 195 def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>; 196 def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>; 197 198// Register classes. 199// 200// FIXME: the register order should be defined in terms of the preferred 201// allocation order... 202// 203def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, 204 (add (sequence "R%u", 0, 9), 205 (sequence "R%u", 12, 28), 206 R10, R11, R29, R30, R31)> { 207} 208 209// Registers are listed in reverse order for allocation preference reasons. 210def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32, 211 (add R7, R6, R5, R4, R3, R2, R1, R0)> ; 212 213def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, 214 (add (sequence "D%u", 0, 4), 215 (sequence "D%u", 6, 13), D5, D14, D15)>; 216 217def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512, 218 (add (sequence "V%u", 0, 31))>; 219 220def VecDblRegs : RegisterClass<"Hexagon", 221 [v128i8, v64i16, v32i32, v16i64], 1024, 222 (add (sequence "W%u", 0, 15))>; 223 224def VectorRegs128B : RegisterClass<"Hexagon", 225 [v128i8, v64i16, v32i32, v16i64], 1024, 226 (add (sequence "V%u", 0, 31))>; 227 228def VecDblRegs128B : RegisterClass<"Hexagon", 229 [v256i8,v128i16,v64i32,v32i64], 2048, 230 (add (sequence "W%u", 0, 15))>; 231 232def VecPredRegs : RegisterClass<"Hexagon", [v512i1], 512, 233 (add (sequence "Q%u", 0, 3))>; 234 235def VecPredRegs128B : RegisterClass<"Hexagon", [v1024i1], 1024, 236 (add (sequence "Q%u", 0, 3))>; 237 238def PredRegs : RegisterClass<"Hexagon", 239 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, 240 (add (sequence "P%u", 0, 3))> 241{ 242 let Size = 32; 243} 244 245let Size = 32 in 246def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; 247 248let Size = 32, isAllocatable = 0 in 249def CtrRegs : RegisterClass<"Hexagon", [i32], 32, 250 (add LC0, SA0, LC1, SA1, 251 P3_0, 252 M0, M1, C6, C7, CS0, CS1, UPCL, UPCH, 253 USR, USR_OVF, UGP, GP, PC)>; 254 255let Size = 64, isAllocatable = 0 in 256def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64, 257 (add C1_0, C3_2, C7_6, C9_8, C11_10, CS, UPC)>; 258 259def VolatileV3 { 260 list<Register> Regs = [D0, D1, D2, D3, D4, D5, D6, D7, 261 R28, R31, 262 P0, P1, P2, P3, 263 M0, M1, 264 LC0, LC1, SA0, SA1, USR, USR_OVF]; 265} 266 267def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a), 268[{ 269 return isPositiveHalfWord(N); 270}]>; 271