| /external/llvm/include/llvm/Target/ |
| D | TargetOpcodes.h | 82 REG_SEQUENCE = 12, enumerator
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | sgpr-copy-duplicate-operand.ll | 5 ; used in an REG_SEQUENCE that also needs to be handled.
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| D | literals.ll | 37 ; Make sure inline literals are folded into REG_SEQUENCE instructions.
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| D | si-lod-bias.ll | 5 ; the wrong register class is used for the REG_SEQUENCE instructions.
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| D | smrd.ll | 47 ; through REG_SEQUENCE
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2012-01-24-RegSequenceLiveRange.ll | 7 ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
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| D | crash.ll | 31 ; PR10520 - REG_SEQUENCE with implicit-def operands.
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| D | reg_sequence.ll | 3 ; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's.
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1586 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE; in getVALUOp()
1670 case AMDGPU::REG_SEQUENCE: in canReadVGPR()
2029 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) { in legalizeOperands()
2121 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc) in legalizeOperands()
2149 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) in legalizeOperands()
2217 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) in legalizeOperands()
2330 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst) in splitSMRD()
2390 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc) in moveSMRDToVALU()
2686 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitUnaryOp()
2752 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitBinaryOp()
[all …]
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| D | R600OptimizeVectorRegisters.cpp | 68 assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE); in RegSeqInfo()
329 if (MI->getOpcode() != AMDGPU::REG_SEQUENCE) { in runOnMachineFunction()
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| D | AMDGPUISelDAGToDAG.cpp | 197 case AMDGPU::REG_SEQUENCE: { in getOperandRegClass()
403 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), in Select()
425 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, in Select()
455 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, in Select()
748 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args); in SelectADD_SUB_I64()
1263 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, in SelectAddrSpaceCast()
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| D | SIFixSGPRCopies.cpp | 344 case AMDGPU::REG_SEQUENCE: { in runOnMachineFunction()
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| D | SIFoldOperands.cpp | 263 if (UseMI->getOpcode() == AMDGPU::REG_SEQUENCE) { in foldOperand()
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| D | SIInstructions.td | 2149 (i64 (REG_SEQUENCE SReg_64,
2626 (REG_SEQUENCE VReg_64,
2646 (REG_SEQUENCE VReg_64,
2656 (REG_SEQUENCE VReg_64,
2720 (REG_SEQUENCE VReg_128,
3102 (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1)
3107 (REG_SEQUENCE VReg_64,
3120 (REG_SEQUENCE SReg_64, $src, sub0,
3126 (REG_SEQUENCE VReg_64,
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| D | SIISelLowering.cpp | 2319 Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) { in PostISelFolding()
2396 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, in wrapAddr64Rsrc()
2408 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1); in wrapAddr64Rsrc()
2444 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops); in buildRSRC()
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| D | AMDGPUInstructions.td | 570 (REG_SEQUENCE RC64,
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 266 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
306 case TargetOpcode::REG_SEQUENCE: in reserveResources()
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| D | InstrEmitter.cpp | 612 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
740 if (Opc == TargetOpcode::REG_SEQUENCE) { in EmitMachineNode()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 56 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
108 case TargetOpcode::REG_SEQUENCE: in reserveResources()
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| D | HexagonBitSimplify.cpp | 405 assert(I.getOpcode() == TargetOpcode::REG_SEQUENCE); in parseRegSequence()
1577 case TargetOpcode::REG_SEQUENCE: in isCopyReg()
1610 case TargetOpcode::REG_SEQUENCE: { in propagateRegCopy()
2132 if (Opc == TargetOpcode::COPY || Opc == TargetOpcode::REG_SEQUENCE) in processBlock()
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| D | HexagonISelDAGToDAG.cpp | 1248 Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, in SelectBitOp()
1257 Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, in SelectBitOp()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 780 return getOpcode() == TargetOpcode::REG_SEQUENCE;
819 case TargetOpcode::REG_SEQUENCE:
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 270 TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32, in SelectInlineAsm()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1599 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createGPRPairNode()
1610 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createSRegPairNode()
1621 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createDRegPairNode()
1632 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQRegPairNode()
1647 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadSRegsNode()
1662 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadDRegsNode()
1677 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadQRegsNode()
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| D | A15SDOptimizer.cpp | 474 TII->get(TargetOpcode::REG_SEQUENCE), Out) in createRegSequence()
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