1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4; This shader has the potential to generated illegal VGPR to SGPR copies if 5; the wrong register class is used for the REG_SEQUENCE instructions. 6 7; CHECK: {{^}}main: 8; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, 15, 0, 0, 0, 0, 0, 0, 0, v{{\[[0-9]:[0-9]\]}} 9 10define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { 11main_body: 12 %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 13 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1 14 %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16) 15 %23 = getelementptr <32 x i8>, <32 x i8> addrspace(2)* %2, i32 0 16 %24 = load <32 x i8>, <32 x i8> addrspace(2)* %23, !tbaa !1 17 %25 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %1, i32 0 18 %26 = load <16 x i8>, <16 x i8> addrspace(2)* %25, !tbaa !1 19 %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5) 20 %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5) 21 %29 = bitcast float %22 to i32 22 %30 = bitcast float %27 to i32 23 %31 = bitcast float %28 to i32 24 %32 = insertelement <4 x i32> undef, i32 %29, i32 0 25 %33 = insertelement <4 x i32> %32, i32 %30, i32 1 26 %34 = insertelement <4 x i32> %33, i32 %31, i32 2 27 %35 = insertelement <4 x i32> %34, i32 undef, i32 3 28 %36 = call <4 x float> @llvm.SI.sampleb.v4i32(<4 x i32> %35, <32 x i8> %24, <16 x i8> %26, i32 2) 29 %37 = extractelement <4 x float> %36, i32 0 30 %38 = extractelement <4 x float> %36, i32 1 31 %39 = extractelement <4 x float> %36, i32 2 32 %40 = extractelement <4 x float> %36, i32 3 33 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %37, float %38, float %39, float %40) 34 ret void 35} 36 37; Function Attrs: nounwind readnone 38declare float @llvm.SI.load.const(<16 x i8>, i32) #1 39 40; Function Attrs: nounwind readnone 41declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 42 43; Function Attrs: nounwind readnone 44declare <4 x float> @llvm.SI.sampleb.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1 45 46declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 47 48attributes #0 = { "ShaderType"="0" } 49attributes #1 = { nounwind readnone } 50 51!0 = !{!"const", null} 52!1 = !{!0, !0, i64 0, i32 1} 53