| /external/llvm/test/CodeGen/AArch64/ |
| D | divrem.ll | 3 ; SDIVREM/UDIVREM DAG nodes are generated but expanded when lowering and
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 204 SDIVREM, UDIVREM, enumerator
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 145 setOperationAction(ISD::SDIVREM, VT, Expand); in InitAMDILLowering()
167 setOperationAction(ISD::SDIVREM, VT, Expand); in InitAMDILLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 186 case ISD::SDIVREM: return "sdivrem"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 2211 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_SDIV()
2212 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_SDIV()
2396 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_SREM()
2397 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_SREM()
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| D | LegalizeVectorOps.cpp | 268 case ISD::SDIVREM: in LegalizeOp()
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| D | LegalizeDAG.cpp | 2346 bool isSigned = Opcode == ISD::SDIVREM; in ExpandDivRemLibCall()
3454 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3473 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
4185 case ISD::SDIVREM: in ConvertNodeToLibcall()
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| D | DAGCombiner.cpp | 2173 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in useDivRem()
2452 (OptimizedDiv.getOpcode() != ISD::SDIVREM)); in visitREM()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 152 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in BPFTargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 154 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); in MSP430TargetLowering()
160 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 129 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
136 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
213 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
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| D | MipsISelLowering.cpp | 426 setTargetDAGCombine(ISD::SDIVREM); in MipsTargetLowering()
479 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : in performDivRemCombine()
818 case ISD::SDIVREM: in PerformDAGCombine()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 246 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
317 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
624 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
1864 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM()
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| D | R600ISelLowering.cpp | 887 case ISD::SDIVREM: { in ReplaceNodeResults()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2595 case ISD::SDIVREM: in Select()
2602 bool isSigned = (Opcode == ISD::SDIVREM || in Select()
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| D | X86ISelLowering.cpp | 722 setOperationAction(ISD::SDIVREM, VT, Expand); in X86TargetLowering()
1789 setOperationAction(ISD::SDIVREM, MVT::i128, Custom); in X86TargetLowering()
18146 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break; in LowerWin64_i128OP()
20223 case ISD::SDIVREM: in ReplaceNodeResults()
27021 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 && in PerformSExtCombine()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 808 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in ARMTargetLowering()
811 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in ARMTargetLowering()
6891 case ISD::SDIVREM: in LowerOperation()
11523 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemLibcall()
11526 bool isSigned = N->getOpcode() == ISD::SDIVREM || in getDivRemLibcall()
11541 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemArgList()
11544 bool isSigned = N->getOpcode() == ISD::SDIVREM || in getDivRemArgList()
11564 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
11566 bool isSigned = (Opcode == ISD::SDIVREM); in LowerDivRem()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1691 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1749 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC, in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1511 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1518 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 373 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 167 setOperationAction(ISD::SDIVREM, VT, Custom); in SystemZTargetLowering()
4343 case ISD::SDIVREM: in LowerOperation()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 238 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in AArch64TargetLowering()
239 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in AArch64TargetLowering()
241 setOperationAction(ISD::SDIVREM, VT, Expand); in AArch64TargetLowering()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 156 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in PPCTargetLowering()
158 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in PPCTargetLowering()
478 setOperationAction(ISD::SDIVREM, VT, Expand); in PPCTargetLowering()
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