| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600ISelLowering.cpp | 45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
342 ISD::SELECT_CC, in LowerBR_CC()
431 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
466 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
488 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
508 ISD::SELECT_CC, in LowerSETCC()
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| D | SIISelLowering.cpp | 56 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SITargetLowering()
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SITargetLowering()
59 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in SITargetLowering()
60 setTargetDAGCombine(ISD::SELECT_CC); in SITargetLowering()
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
400 case ISD::SELECT_CC: { in PerformDAGCombine()
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| D | AMDILISelLowering.cpp | 170 setOperationAction(ISD::SELECT_CC, VT, Expand); in InitAMDILLowering()
289 case ISD::SELECT_CC: in computeMaskedBitsForTargetNode()
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2010-04-09-NeonSelect.ll | 2 ; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values.
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.h | 29 SELECT_CC, enumerator
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| D | BPFISelLowering.cpp | 109 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in BPFTargetLowering()
178 case ISD::SELECT_CC: in LowerOperation()
507 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); in LowerSELECT_CC()
518 case BPFISD::SELECT_CC: in getTargetNodeName()
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| D | BPFInstrInfo.td | 43 def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 364 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
367 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
369 "# SELECT_CC PSEUDO!",
1207 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1210 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1213 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1215 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1217 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1219 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1221 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
171 setTargetDAGCombine(ISD::SELECT_CC); in R600TargetLowering()
601 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
1169 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
1226 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
1250 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
1252 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1861 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1870 return DAG.getNode(ISD::SELECT_CC, dl, N->getValueType(0), in PerformDAGCombine()
[all …]
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| D | SIISelLowering.cpp | 101 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in SITargetLowering()
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in SITargetLowering()
103 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in SITargetLowering()
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in SITargetLowering()
195 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); in SITargetLowering()
262 setTargetDAGCombine(ISD::SELECT_CC); in SITargetLowering()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 361 SELECT_CC, enumerator
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 62 SELECT_CC, enumerator
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| D | MSP430ISelLowering.cpp | 112 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in MSP430TargetLowering()
113 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in MSP430TargetLowering()
194 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
980 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); in LowerSETCC()
999 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); in LowerSELECT_CC()
1151 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; in getTargetNodeName()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 108 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N, ResNo); break; in SoftenFloatResult()
661 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in SoftenFloatRes_SELECT_CC()
744 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break; in SoftenFloatOperand()
789 case ISD::SELECT_CC: in CanSkipSoftenFloatOperand()
988 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandFloatResult()
1493 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; in ExpandFloatOperand()
1732 case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break; in PromoteFloatOperand()
1792 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), in PromoteFloatOp_SELECT_CC()
1888 case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break; in PromoteFloatResult()
2099 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), in PromoteFloatRes_SELECT_CC()
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| D | LegalizeTypesGeneric.cpp | 552 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
554 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
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| D | SelectionDAGDumper.cpp | 216 case ISD::SELECT_CC: return "select_cc"; in getOperationName()
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| D | LegalizeDAG.cpp | 1261 case ISD::SELECT_CC: in LegalizeOp()
1264 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : in LegalizeOp()
1273 if (Node->getOpcode() == ISD::SELECT_CC) in LegalizeOp()
3799 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, in ExpandNode()
3806 case ISD::SELECT_CC: { in ExpandNode()
3867 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), in ExpandNode()
3872 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, in ExpandNode()
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| D | LegalizeVectorTypes.cpp | 65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; in ScalarizeVectorResult()
345 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(), in ScalarizeVecRes_SELECT_CC()
595 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in SplitVectorResult()
2013 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; in WidenVectorResult()
2856 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in WidenVecRes_SELECT_CC()
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| D | LegalizeIntegerTypes.cpp | 76 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; in PromoteIntegerResult()
584 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in PromoteIntRes_SELECT_CC()
893 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; in PromoteIntegerOperand()
1297 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandIntegerResult()
2664 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; in ExpandIntegerOperand()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 238 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in PPCTargetLowering()
239 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in PPCTargetLowering()
441 setOperationAction(ISD::SELECT_CC, VT, Promote); in PPCTargetLowering()
442 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); in PPCTargetLowering()
862 setTargetDAGCombine(ISD::SELECT_CC); in PPCTargetLowering()
7980 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
9467 N->getOpcode() == ISD::SELECT_CC) { in DAGCombineTruncBoolExt()
9510 N->getOperand(0).getOpcode() != ISD::SELECT_CC && in DAGCombineTruncBoolExt()
9517 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) && in DAGCombineTruncBoolExt()
9522 N->getOperand(1).getOpcode() != ISD::SELECT_CC && in DAGCombineTruncBoolExt()
[all …]
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 145 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in NVPTXTargetLowering()
146 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in NVPTXTargetLowering()
147 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); in NVPTXTargetLowering()
148 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand); in NVPTXTargetLowering()
149 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand); in NVPTXTargetLowering()
150 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in NVPTXTargetLowering()
151 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in NVPTXTargetLowering()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 173 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC}) in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1557 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1558 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1559 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1560 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1572 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
2944 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, in LowerOperation()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 127 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in AArch64TargetLowering()
128 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in AArch64TargetLowering()
129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in AArch64TargetLowering()
130 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in AArch64TargetLowering()
168 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in AArch64TargetLowering()
277 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); in AArch64TargetLowering()
348 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand); in AArch64TargetLowering()
381 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand); in AArch64TargetLowering()
553 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand); in AArch64TargetLowering()
676 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); in addTypeForNEON()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 280 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in MipsTargetLowering()
281 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in MipsTargetLowering()
328 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in MipsTargetLowering()
329 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in MipsTargetLowering()
875 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); in LowerOperation()
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