Home
last modified time | relevance | path

Searched refs:SETUGE (Results 1 – 25 of 37) sorted by relevance

12

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h854 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
881 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/external/llvm/lib/CodeGen/
DAnalysis.cpp176 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
192 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
207 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td51 defm GE_U : ComparisonInt<SETUGE, "ge_u">;
DWebAssemblyISelLowering.cpp132 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUInstructions.td59 case ISD::SETOGE: case ISD::SETUGE:
DAMDILISelLowering.cpp136 setOperationAction(ISD::SETUGE, VT, Expand); in InitAMDILLowering()
DR600Instructions.td441 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td68 IntRegs:$fval, SETUGE)),
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp201 case ISD::SETUGE: in softenSetCCOperands()
1461 case ISD::SETUGE: in SimplifySetCC()
1484 case ISD::SETUGE: in SimplifySetCC()
1631 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
1663 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
1761 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
1774 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
1848 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
2072 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
DSelectionDAGDumper.cpp341 case ISD::SETUGE: return "setuge"; in getOperationName()
DLegalizeIntegerTypes.cpp965 case ISD::SETUGE: in PromoteSetCCOperands()
2749 case ISD::SETUGE: LowCC = ISD::SETUGE; break; in IntegerExpandSetCCOperands()
2782 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || in IntegerExpandSetCCOperands()
2814 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break; in IntegerExpandSetCCOperands()
/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td1010 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUGE),
1057 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUGE),
1129 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGE)),
1150 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGE)),
1171 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGE)),
DPPCInstrInfo.td2901 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3092 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3120 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3160 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3188 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3215 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3246 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3287 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3313 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3334 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
[all …]
DPPCISelDAGToDAG.cpp2110 case ISD::SETUGE: in getPredicateForSetCC()
2134 case ISD::SETUGE: in getCRIdxForSetCC()
2167 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
2211 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
DPPCInstrVSX.td962 def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)),
983 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
1082 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp596 case ISD::SETUGE: in EmitInstrWithCustomInserter()
DBPFInstrInfo.td79 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1139 case ISD::SETUGE: in CombineFMinMaxLegacy()
1706 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE); in LowerUDIVREM64()
1712 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
1789 ISD::SETUGE); in LowerUDIVREM()
1795 ISD::SETUGE); in LowerUDIVREM()
DAMDGPUInstructions.td110 def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp193 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in MipsSETargetLowering()
198 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in MipsSETargetLowering()
289 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAIntType()
325 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAFloatType()
966 case ISD::SETUGE: return !IsV216; in isLegalDSPCondCode()
DMipsDSPInstrInfo.td1399 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1412 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td582 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
969 (setcc node:$lhs, node:$rhs, SETUGE)>;
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1068 case ISD::SETUGE: in changeIntCCToAArch64CC()
1120 case ISD::SETUGE: in changeFPCCToAArch64CC()
1162 case ISD::SETUGE: in changeVectorFPCCToAArch64CC()
1457 case ISD::SETUGE: in getAArch64Cmp()
1483 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getAArch64Cmp()
8979 (Op == ISD::UMAX && CC != ISD::SETUGT && CC != ISD::SETUGE) || in performAcrossLaneMinMaxReductionCombine()
8983 CC != ISD::SETUGT && CC != ISD::SETUGE && CC != ISD::SETGT && in performAcrossLaneMinMaxReductionCombine()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp836 case ISD::SETUGE: in EmitCMP()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1322 case ISD::SETUGE: return ARMCC::HS; in IntCCToARMCC()
1347 case ISD::SETUGE: CondCode = ARMCC::PL; break; in FPCCToARMCC()
3308 case ISD::SETUGE: in getARMCmp()
3324 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getARMCmp()
3523 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE || in checkVSELConstraints()
3546 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE || in checkVSELConstraints()
4642 case ISD::SETUGE: Swap = true; // Fallthrough in LowerVSETCC()
4678 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; in LowerVSETCC()

12