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Searched refs:SIGN_EXTEND_INREG (Results 1 – 25 of 32) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); in R600TargetLowering()
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
[all …]
DSIISelLowering.cpp112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal); in SITargetLowering()
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom); in SITargetLowering()
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom); in SITargetLowering()
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal); in SITargetLowering()
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in SITargetLowering()
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom); in SITargetLowering()
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in SITargetLowering()
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in SITargetLowering()
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom); in SITargetLowering()
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in SITargetLowering()
[all …]
DAMDGPUISelLowering.cpp618 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
645 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
1467 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode), in LowerLOAD()
2289 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp); in LowerSIGN_EXTEND_INREG()
2528 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom, in PerformDAGCombine()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in BPFTargetLowering()
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in BPFTargetLowering()
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in BPFTargetLowering()
147 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); in BPFTargetLowering()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h410 SIGN_EXTEND_INREG, enumerator
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); in InitAMDILLowering()
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom); in InitAMDILLowering()
218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); in InitAMDILLowering()
DAMDGPUISelLowering.cpp92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp84 case ISD::SIGN_EXTEND_INREG: in PromoteIntegerResult()
456 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_INT_EXTEND()
551 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_SADDSUBO()
635 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), in PromoteIntRes_SIGN_EXTEND_INREG()
791 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), in PromoteIntRes_XMULO()
1154 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), in PromoteIntOp_SIGN_EXTEND()
1324 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; in ExpandIntegerResult()
2357 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND()
2371 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, in ExpandIntRes_SIGN_EXTEND_INREG()
2384 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND_INREG()
DLegalizeVectorOps.cpp326 case ISD::SIGN_EXTEND_INREG: in LegalizeOp()
700 case ISD::SIGN_EXTEND_INREG: in Expand()
DSelectionDAGDumper.cpp243 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; in getOperationName()
DDAGCombiner.cpp1001 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
1013 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, in SExtPromoteOperand()
1404 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); in visit()
1778 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitADD()
1957 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { in visitSUB()
4607 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) in visitSRA()
4608 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, in visitSRA()
6012 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, in visitSIGN_EXTEND()
6018 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op, in visitSIGN_EXTEND()
6736 if (Opc == ISD::SIGN_EXTEND_INREG) { in ReduceLoadWidth()
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DLegalizeVectorTypes.cpp62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; in ScalarizeVectorResult()
325 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT, in ScalarizeVecRes_VSELECT()
607 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; in SplitVectorResult()
2010 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; in WidenVectorResult()
DLegalizeTypes.h227 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, in SExtPromotedInteger()
DSelectionDAG.cpp2234 case ISD::SIGN_EXTEND_INREG: { in computeKnownBits()
2552 case ISD::SIGN_EXTEND_INREG: in ComputeNumSignBits()
3591 case ISD::SIGN_EXTEND_INREG: { in getNode()
3804 case ISD::SIGN_EXTEND_INREG: in getNode()
5525 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && in getNode()
6988 case ISD::SIGN_EXTEND_INREG: in UnrollVectorOp()
DLegalizeDAG.cpp997 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, in LegalizeLoadOps()
1176 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, in LegalizeLoadOps()
1251 case ISD::SIGN_EXTEND_INREG: { in LegalizeOp()
3115 case ISD::SIGN_EXTEND_INREG: { in ExpandNode()
DTargetLowering.cpp822 case ISD::SIGN_EXTEND_INREG: { in SimplifyDemandedBits()
1504 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in SimplifySetCC()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp162 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); in WebAssemblyTargetLowering()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal); in NVPTXTargetLowering()
162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in NVPTXTargetLowering()
163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in NVPTXTargetLowering()
164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); in NVPTXTargetLowering()
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in NVPTXTargetLowering()
4103 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) { in IsMulWideOperandDemotable()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp136 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in MSP430TargetLowering()
1010 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, in LowerSIGN_EXTEND()
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp533 IndexOpcode == ISD::SIGN_EXTEND_INREG) in shouldUseLA()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
486 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); in PPCTargetLowering()
645 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal); in PPCTargetLowering()
646 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in PPCTargetLowering()
647 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in PPCTargetLowering()
648 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in PPCTargetLowering()
7545 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op, in LowerSIGN_EXTEND_INREG()
7549 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op, in LowerSIGN_EXTEND_INREG()
7998 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1504 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
1505 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
1506 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp334 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in MipsTargetLowering()
402 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in MipsTargetLowering()
403 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in MipsTargetLowering()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp1514 case ISD::SIGN_EXTEND_INREG: in isValueExtension()
DHexagonISelLowering.cpp1607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in HexagonTargetLowering()
2812 case ISD::SIGN_EXTEND_INREG: in isPositiveHalfWord()

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